High speed, parallel configuration of multiple field programmable gate arrays
View Patent ↗Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.
1. A method of configuring a system having at least one host computing system and one or more field programmable gate arrays, the method comprising:
using a host processor, storing a first configuration bit image for a first application in a host memory;
configuring the one or more field programmable gate arrays with a communication functionality, the communication functionality provided in a second configuration bit image stored in a nonvolatile memory;
using the host processor, transmitting a first message to one or more primary field programmable gate arrays, the first message comprising a first memory address of the first configuration bit image in the host memory;
using a DMA engine, each primary field programmable gate array accessing the host memory and obtaining the first configuration bit image; and
using the first configuration bit image, each primary field programmable gate array self-configuring for the first application.
2. The method of claim 1 , further comprising:
using the primary field programmable gate array, transmitting the first configuration bit image to one or more secondary field programmable gate arrays.
3. The method of claim 2 , further comprising:
using the first configuration bit image transmitted from the primary field programmable gate array, configuring the secondary field programmable gate arrays.
4. The method of claim 2 , wherein the first configuration bit image is transmitted to the one or more secondary field programmable gate arrays through a plurality of JTAG communication lines.
5. The method of claim 1 , wherein the communication functionality is PCIe.
6. The method of claim 1 , wherein the first message further comprises a file size of the first configuration bit image.
7. The method of claim 1 , further comprising:
configuring the DMA engine in the one or more primary field programmable gate arrays, the DMA engine functionality provided in a third configuration bit image stored in the nonvolatile memory.
8. The method of claim 1 , wherein the first message is transmitted to the one or more primary field programmable gate arrays through a plurality of PCIe communication lines.
9. The method of claim 1 , further comprising:
using the host processor, transmitting a second message to the one or more primary field programmable gate arrays, the second message comprising a second memory address of a third configuration bit image for a second application in the host memory;
using the DMA engine, each primary field programmable gate array accessing the host memory and obtaining the third configuration bit image; and
using the third configuration bit image, each primary field programmable gate array self-reconfiguring for the second application.
10. A system comprising:
a host computing system comprising a host processor and a host memory, a first configuration bit image for a first application stored in the host memory, the host processor adapted to transmit a first message comprising a first memory address of the first configuration bit image in the host memory;
one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality; and
a plurality of primary field programmable gate arrays, each primary field programmable gate array coupled to the host processor and coupled to a nonvolatile memory of the one or more nonvolatile memories, each primary field programmable gate array configured for the communication functionality using the second configuration bit image, each primary field programmable gate array having a DMA engine and, in response to the first message, configured to use the DMA engine to access the host memory, obtain the first configuration bit image, and to self-configure for the first application using the first configuration bit image.
11. The system of claim 10 , further comprising:
a plurality of secondary field programmable gate arrays coupled to a primary field programmable gate array of the plurality of primary field programmable gate arrays, the primary field programmable gate array configured to transmit the first configuration bit image to one or more secondary field programmable gate arrays of the plurality of secondary field programmable gate arrays.
12. The system of claim 11 , wherein each secondary field programmable gate array of the plurality of secondary field programmable gate arrays is configured for the first application using the first configuration bit image.
13. The system of claim 11 , further comprising:
a plurality of JTAG communication lines coupling the primary field programmable gate array to the one or more secondary field programmable gate arrays for transmission of the first configuration bit image.
14. The system of claim 11 , further comprising:
at least one tertiary field programmable gate array configured as a non-blocking crossbar switch and coupled to the plurality of primary field programmable gate arrays and to the plurality of secondary field programmable gate arrays.
15. The system of claim 10 , further comprising:
a PCIe switch; and
a plurality of PCIe communication lines coupling the plurality of primary field programmable gate arrays through the PCIe switch to the host processor.
16. The system of claim 15 , wherein the communication functionality is PCIe.
17. The system of claim 15 , wherein the first message is transmitted to the plurality of primary field programmable gate arrays through the plurality of PCIe communication lines.
18. The system of claim 10 , wherein the first message further comprises a file size of the first configuration bit image.
19. The system of claim 10 , wherein the plurality of primary field programmable gate arrays are configured for the DMA engine functionality using a third configuration bit image stored in the nonvolatile memory.
20. The system of claim 10 , wherein each primary field programmable gate array of the plurality of primary field programmable gate arrays, in response to a second message comprising a memory address of a third configuration bit image in the host memory, is configured to access the host memory, obtain the third configuration bit image, and reconfigure using the third configuration bit image for a second application.
21. A system comprising:
a PCIe switch;
a plurality of PCIe communication lines coupled to the PCIe switch;
a host computing system coupled to at least one PCIe communication line of the plurality of PCIe communication lines, the host computing system comprising a host processor and a host memory, a first configuration bit image for an application stored in the host memory, the host processor adapted to transmit a message on the at least one PCIe communication line, the message comprising a memory address of the first configuration bit image in the host memory;
one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality;
a plurality of JTAG communication lines;
a plurality of primary field programmable gate arrays, each primary field programmable gate array coupled to a corresponding PCIe communication line of the plurality of PCIe communication lines and to one or more corresponding JTAG communication lines of the plurality of JTAG communication lines; each primary field programmable gate array coupled to a nonvolatile memory of the one or more nonvolatile memories, each primary field programmable gate array configured for the communication functionality using the second configuration bit image, each primary field programmable gate array having a DMA engine and, in response to the message, configured to use the DMA engine to access the host memory, obtain the first configuration bit image, to self-configure for the application using the first configuration bit image, and to transmit the first configuration bit image over the one or more corresponding JTAG communication lines; and
a plurality of secondary field programmable gate arrays, each secondary field programmable gate array coupled to a JTAG communication line of the plurality of JTAG communication lines, each secondary field programmable gate configured for the application using the first configuration bit image transmitted over the plurality of JTAG communication lines.