System and method for independent, direct and parallel communication among multiple field programmable gate arrays
View Patent ↗Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. Once base DMA registers have been initialized for a selected application, no further involvement by the host computing system is involved for the duration of the selected application.
1. A system couplable to a host computing system, the system comprising:
a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines;
a plurality of memory circuits; and
a plurality of field programmable gate arrays, each field programmable gate array coupled to the PCIe communication network and to at least one memory circuit of the plurality of memory circuits, each field programmable gate array configured to generate a plurality of data transfers to any other field programmable gate array of the plurality of field programmable gate arrays, each field programmable gate array further configured to generate a data packet, for each data transfer of the plurality of data transfers, comprising a data transfer header having a designation of a first memory address and a stream number.
2. The system of claim 1 , further comprising:
at least one tertiary field programmable gate array configured as a non-blocking crossbar switch and coupled to the plurality of field programmable gate arrays.
3. The system of claim 2 , wherein each field programmable gate array is further configured to perform one or more data transfers through the PCIe communication network or through the nonblocking crossbar switch, and wherein each field programmable gate array is further configured to perform at least some data transfers of the plurality of data transfers in parallel and directly between or among the plurality of field programmable gate arrays.
4. The system of claim 1 , wherein each field programmable gate array is further configured to include a file size designation in each data transfer header.
5. The system of claim 1 , wherein prior to commencement of a computing application to be performed by one or more field programmable gate arrays of the plurality of field programmable gate arrays, the host computing system is adapted to transmit a plurality of DMA register messages to the one or more field programmable gate arrays, each DMA register message designating a memory address of the plurality of memory circuits, a file size, and the stream number.
6. The system of claim 5 , wherein each DMA register maintains its designations until another DMA register message changing the designations is received.
7. The system of claim 1 , wherein each field programmable gate array is further configured to include a designation of a second memory address and a tie stream number in one or more data transfer headers.
8. The system of claim 7 , wherein in response to receiving a data transfer including the designation of the second memory address and the tie stream number, each field programmable gate array is further configured to forward the data transferred to the second memory address and the tie stream number.
9. The system of claim 1 , further comprising:
a plurality of data communication lines coupling the plurality of field programmable gate arrays in series, and wherein each field programmable gate array is further configured to perform one or more data transfers directly through the plurality of data communication lines.
10. A system comprising:
a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines;
a host computing system coupled to the PCIe communication network;
a nonblocking crossbar switch;
a plurality of memory circuits; and
a plurality of field programmable gate arrays, each field programmable gate array coupled to the PCIe communication network, to the nonblocking crossbar switch, and to at least one memory circuit of the plurality of memory circuits, each field programmable gate array configured to generate a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, each field programmable gate array further configured to generate a data packet, for each data transfer of the plurality of data transfers, comprising a data transfer header having a designation of a first memory address and a stream number.
11. The system of claim 10 , wherein each field programmable gate array is further configured to perform one or more data transfers through the PCIe communication network or through the nonblocking crossbar switch and wherein each field programmable gate array is further configured to perform at least some data transfers of the plurality of data transfers in parallel and directly between or among the plurality of field programmable gate arrays.
12. The system of claim 10 , wherein each data transfer header further comprises a file size designation.
13. The system of claim 10 , wherein prior to commencement of a computing application to be performed by one or more field programmable gate arrays of the plurality of field programmable gate, the host computing system is adapted to transmit a plurality of DMA register messages to the one or more field programmable gate arrays, each DMA register message designating a selected memory address of the plurality of memory circuits, a selected file size, and a selected stream number.
14. The system of claim 13 , wherein each DMA register maintains its designations until another DMA register message changing the designations is received.
15. The system of claim 10 , wherein each field programmable gate array is further configured to include a designation of a second memory address and a tie stream number in one or more data transfer headers.
16. The system of claim 15 , wherein in response to receiving a data transfer including the designation of the second memory address and the tie stream number, each field programmable gate array is further configured to forward the data transferred to the second memory address and the tie stream number.
17. The system of claim 10 , wherein the nonblocking crossbar switch is implemented using a selected field programmable gate array of the plurality of field programmable gate arrays.
18. The system of claim 10 , wherein the nonblocking crossbar switch is implemented using the PCIe switch or a second PCIe switch.
19. A system comprising:
a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines;
a host computing system coupled to the PCIe communication network;
a first field programmable gate array configured as a nonblocking crossbar switch;
a plurality of memory circuits; and
a plurality of second field programmable gate arrays, each second field programmable gate array coupled to the PCIe communication network, to the first field programmable gate array configured as a nonblocking crossbar switch, and to at least one memory circuit of the plurality of memory circuits, each second field programmable gate array configured to generate a plurality of data transfers to and from the host computing system and any other second field programmable gate array of the plurality of second field programmable gate arrays, each second field programmable gate array further configured to generate a data packet, for each data transfer of the plurality of data transfers, comprising a data transfer header having a designation of a first memory address, a file size, and a stream number, and each second field programmable gate array further configured to perform at least some data transfers of the plurality of data transfers in parallel and directly between or among the plurality of second field programmable gate arrays.