IP Library Granted Patent US 9,768,134
Granted Patent B2
US 9,768,134 · App. 14/608,466 · Granted Sep 19, 2017

Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects

Inventors: Anilkumar Chandolu (Boise, ID); Kenneth N. Hagen (Boise, ID)
Assignee: Micron Technology, Inc.
H01L24/13H01L22/20H01L24/03H01L24/05H01L25/0657H01L25/50H01L22/14H01L24/02H01L24/11H01L24/16H01L24/29H01L24/32H01L24/81H01L24/83H01L24/94H01L2224/0239H01L2224/02215H01L2224/0345H01L2224/0362H01L2224/03452H01L2224/03614H01L2224/03914H01L2224/03916H01L2224/03921H01L2224/0401H01L2224/05017H01L2224/05018H01L2224/05025H01L2224/0557H01L2224/0569H01L2224/05147H01L2224/05166H01L2224/05187H01L2224/05558H01L2224/05565H01L2224/05583H01L2224/05647H01L2224/05687H01L2224/05688H01L2224/1132H01L2224/1145H01L2224/1147H01L2224/11424H01L2224/11452H01L2224/11462H01L2224/11464H01L2224/11612H01L2224/11614H01L2224/11622H01L2224/11632H01L2224/13021H01L2224/13025H01L2224/13147H01L2224/16146H01L2224/2919H01L2224/2929H01L2224/29191H01L2224/29387H01L2224/32145H01L2224/73204H01L2224/81203H01L2224/81424H01L2224/81447H01L2224/8388H01L2224/83102H01L2224/83104H01L2224/83862H01L2224/94H01L2225/06513H01L2225/06541H01L2225/06596H01L2924/01022H01L2924/01029
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Quick Facts
Patent No.
US 9,768,134
App. No.
14/608,466
Granted
Sep 19, 2017
Kind
B2
Abstract

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Claims (38)

1. A method of forming a conductive material on a semiconductor device, the method comprising:

removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate and exposing a surface of a conductive material underlying the conductive pad;

forming a seed material at least within a bottom of the aperture and over the dielectric material;

forming a protective material over the seed material within the aperture; and

forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture.

2. The method of claim 1 , wherein forming a seed material at least within a bottom of the aperture comprises forming a conductive seed material directly on and in contact with the conductive material.

3. The method of claim 1 , wherein removing at least a portion of a conductive pad comprises removing only a portion of the conductive pad, and further comprising forming the seed material on a remaining portion of the conductive pad.

4. The method of claim 1 , wherein forming a seed material at least within a bottom of the aperture and over the dielectric material comprises:

forming a titanium-containing material within the aperture and over the dielectric material and the exposed surface of the conductive material; and

forming a copper-containing material over the titanium-containing material.

5. The method of claim 1 , wherein forming a seed material at least within a bottom of the aperture comprises forming the seed material in electrical communication with a through-substrate conductive via extending through the substrate.

6. The method of claim 1 , wherein forming a conductive pillar comprises forming the conductive pillar to comprise the same material as at least a portion of the seed material.

7. The method of claim 1 , further comprising probe testing the semiconductor device prior to removing at least a portion of the conductive pad.

8. A method of forming an electrical connection between adjacent semiconductor devices, the method comprising:

electrically testing interconnects of a conductive pad on a semiconductor device by contacting the conductive pad with a probe of a probe card;

forming a seed material over a conductive material underlying the conductive pad;

forming a protective material over at least portions of the seed material;

exposing a portion of the seed material through an opening in the protective material;

forming a conductive pillar in contact with the exposed portion of the seed material; and

contacting the conductive pillar with a conductive element of another semiconductor device.

9. The method of claim 8 , further comprising forming another conductive pad over the conductive pad after electrically testing interconnects of the conductive pad before forming the seed material.

10. The method of claim 9 , wherein forming another conductive pad over the conductive pad after electrically testing interconnects of the conductive pad comprises forming a copper material over the conductive pad to partially fill an aperture in a dielectric material over the substrate.

11. The method of claim 8 , further comprising removing at least a portion of the conductive pad after electrically testing interconnects of the conductive pad before forming the seed material.

12. The method of claim 8 , further comprising removing all of the conductive pad after electrically testing interconnects of the conductive pad and further comprising forming the seed material directly on the conductive material.

13. The method of claim 8 , wherein contacting the conductive pillar with a conductive element of another semiconductor device comprises contacting the conductive pillar with a conductive element of a logic die.

14. The method of claim 1 , further comprising selecting the protective material to comprise a polyimide, silicon dioxide, silicon nitride, tetraethylorthosilicate, borophosphosilicate, or a polymer.

15. The method of claim 4 , further comprising:

forming the titanium-containing material to have a thickness between about 50 Å and about 1,000 Å; and

and forming the copper-containing material to have a thickness between about 1,000 Å and about 3,000 Å.

16. The method of claim 1 , wherein removing at least a portion of a conductive pad comprises removing at least a portion of a damaged conductive pad.

17. The method of claim 1 , further comprising removing portions of the seed material overlying the dielectric material after forming the conductive pillar.

18. The method of claim 8 , wherein contacting the conductive pillar with a conductive element of another semiconductor device comprises contacting the conductive pillar with a bond pad of the another semiconductor device, the bond pad in contact with a conductive plug.

19. The method of claim 8 , wherein forming a conductive pillar in contact with the exposed portion of the seed material comprises forming at least a portion of the conductive pillar within the opening.

20. A method of forming a conductive material on a semiconductor device, the method comprising:

removing at least a portion of a conductive pad within a bottom portion of an aperture in a dielectric material over a substrate;

forming another conductive pad within the aperture and directly on and contacting a portion of the conductive pad remaining in the bottom portion of the aperture after removing the at least a portion of the conductive pad;

forming a seed material at least within the bottom portion of the aperture and over the dielectric material and the another conductive pad; and

forming a conductive pillar in contact with the seed material.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2015
From: CHANDOLU, ANILKUMAR; HAGEN, KENNETH N.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 034842/0320 →
Continuity (1)
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