Memory controller for a network on a chip device

1. A memory controller for a processing device containing a plurality of computing resources, comprising:

a first interface to couple the memory controller to a router, the first interface being configured to transmit and receive packets each comprising a header, the header containing a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol;

a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory associated with the memory controller; and

a controller core coupled to the first interface, the controller core being configured to:

decode a packet received at the first interface; and

perform an operation specified in the received packet,

wherein the network protocol specifies that the routable address includes a device identifier for the processing device, a cluster identifier for a cluster in which the memory is located, and a memory address pointing to a memory location in the memory associated with the memory controller,

wherein the packets are received from the computing resources, and the computing resources include a device controller for the processing device, cluster controllers for all clusters on the processing device, all other memory controllers of the processing device, and all processing engines on the processing device in other clusters.

2. The memory controller of claim 1 , wherein the packet opcode in the received packet specifies a read operation, and the network protocol specifies that for a read operation the received packet contains a payload that contains a return address, to perform the operation specified in the received packet, the controller core is further configured to:

read data from the memory address contained within the received packet,

place the data in a new packet with a destination address contained within the received packet; and

send the new packet to the first interface to be queued for transmission.

3. The memory controller of claim 1 , wherein the packet opcode in the received packet specifies a write operation, and the network protocol specifies that for a write operation the received packet contains a payload that contains payload data to be written to memory, and to perform the operation specified in the received packet, the controller core is further configured to write the payload data to the memory location.

4. The memory controller of claim 1 , further comprising a second interface to be coupled to a plurality of processing engines within the cluster in which the memory controller is located, the second interface being configured to provide direct memory access to the plurality of processing engines within the cluster in which the memory controller is located.

5. The memory controller of claim 1 , wherein the first interface is configured to support memory access by the plurality of processing engines within the cluster in which the memory controller is located via packet data communication.

6. The memory controller of claim 1 , wherein the first interface includes a first queue to buffer received packets and a second queue to buffer packets to be sent out.

7. The memory controller of claim 1 , wherein the controller core comprises a pipeline for performing operations.

8. A processing device, comprising

a top level router comprising a plurality of high speed communication interfaces to communicate data to other devices external of the processing device;

a device controller coupled to the top level router to control operation of the top level router; and

a plurality of clusters of processing engines, each cluster having:

a cluster controller,

one or more cluster memories each having a memory controller, and

a plurality of processing engines,

wherein the memory controller for at least one of the one or more cluster memories is a smart memory controller, the smart memory controller comprises:

a first interface to be coupled to a router, the first interface being configured to transmit and receive packets each comprising a header, the header containing a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol;

a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory associated with the smart memory controller; and

a controller core coupled to the first interface, the controller core being configured to:

decode a packet received at the first interface; and

perform an operation specified in the received packet;

wherein the device controller, each cluster controller, all memory controllers other than the smart memory controller and all processing engines in clusters other than the cluster in which the smart memory controller is located are configured to address any memory location in the memory associated with the smart memory controller using the packets.

9. The processing device of claim 8 , wherein the network protocol specifies that the routable address includes a device identifier for the processing device, a cluster identifier for the cluster in which the smart memory controller is located, and a memory address pointing to a memory location in the memory associated with the smart memory controller.

10. The processing device of claim 9 , wherein the packet opcode in the received packet specifies a read operation, and the network protocol specifies that for a read operation the received packet contains a payload that contains a return address, to perform the operation specified in the received packet, the controller core is further configured to:

read data from the memory address contained within the received packet,

place the data in a new packet with a destination address contained within the received packet; and

send the new packet to the first interface to be queued for transmission.

11. The processing device of claim 10 , wherein the packet opcode in the received packet specifies a write operation, and the network protocol specifies that for a write operation the received packet contains a payload that contains payload data to be written to memory, and to perform the operation specified in the received packet, the controller core is further configured to write the payload data to the memory location.

12. The processing device of claim 8 , wherein the smart memory controller further comprises a second interface coupled to the plurality of processing engines within the cluster in which the smart memory controller is located, and the second interface is configured to provide direct memory access to these plurality of processing engines.

13. The processing device of claim 12 , wherein the first interface is also configured to support memory access by the plurality of processing engines within the cluster in which the smart memory controller is located via packet data communication.

14. A method for operating a memory controller for a processing device containing a plurality of computing resources, comprising:

receiving a packet on a first interface of the memory controller, the first interface being coupled to a router and configured to transmit and receive packets each comprising a header, the header containing a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol;

decoding the received packet to determine a memory address to be accessed and an operation specified in the received packet, wherein the memory address points to a memory location in a memory associated with the memory controller and the operation is specified by the packet opcode; and

performing the operation specified in the received packet,

wherein the network protocol specifies that the routable address includes a device identifier for the processing device, a cluster identifier for a cluster in which the memory is located, and the memory address to be accessed,

wherein the packets are received from the computing resources, and the computing resources include a device controller for the processing device, cluster controllers for all clusters on the processing device, all other memory controllers of the processing device, and all processing engines on the processing device in other clusters.

15. The method of claim 14 , wherein the packet opcode in the received packet specifies a read operation, and the network protocol specifies that for a read operation the received packet contains a payload that contains a return address, and performing the operation specified in the received packet further comprises:

reading data from the memory address contained within the received packet,

placing the data in a new packet with a destination address contained within the received packet; and

sending the new packet to the first interface to be queued for transmission.

16. The method of claim 14 , wherein the packet opcode in the received packet specifies a write operation, and the network protocol specifies that for a write operation the received packet contains a payload that contains payload data to be written to memory, and performing the operation specified in the received packet further comprising writing the payload data to the memory location.

17. The method of claim 14 , further comprising receiving memory access requests on a second interface from a plurality of processing engines within the cluster in which the memory controller is located, the second interface being configured to provide direct memory access to the plurality of processing engines within the cluster in which the memory controller is located.

18. The method of claim 14 , further comprising receiving memory access packets on the first interface from the plurality of processing engines within the cluster in which the memory controller is located.

19. The method of claim 14 , further comprising buffering packets received from the router in a first queue of the first interface and buffering packets to be sent to the router in a second queue of the first interface.

20. The method of claim 14 , wherein the operation specified in the received packet is performed in a pipeline.