Patent Assignment
Reel/Frame 044637/0011
Security Interest
Recorded: 2017-10-27
Pages: 36
Assignor
KNUEDGE INCORPORATED
Executed: 2017-10-26
Assignee
XL INNOVATE FUND, LP
3555 ALAMEDA DE LAS PULGAS, 2ND FLOOR, MENLO PARK, CALIFORNIA, 94025
Covered Properties
(98)
Mobile Brain-Based Device for Use in a Real World Environment
Mobile Brain-Based Device Having a Simulated Nervous System Based on the Hippocampus
Neural Modeling and Brain-Based Devices Using Special Purpose Processor
Addressing Scheme for Neural Modeling and Brain-Based Devices Using Special Purpose Processor
Neural Segmentation of an Input Signal and Applications Using Simulated Neurons, and a Phase Modulator
Constant Memory Implementation of a Phase-Model Neural Network
Neural Network for Clustering Input Data Based on a Gaussian Mixture Model
Competitive Bcm Learning Rule for Identifying Features
Systems and Methods Using Neural Networks to Reduce Noise in Audio Signals
Neural Processing Unit
Context Aware Device Execution for Simulating Neural Networks in Compute Unified Device Architecture
Patent:
8,626,700 →
Application:
13/097,615 →
Speaker Segmentation in Noisy Conversational Speech
Patent:
8,543,402 →
Application:
13/097,620 →
Denoising an Audio Signal Using Local Formant Information
Patent:
8,897,461 →
Application:
13/097,627 →
Audio Filter Bank Design
Patent:
8,756,265 →
Application:
13/097,633 →
System and Method for Processing Sound Signals Implementing a Spectral Motion Transform
System And Method For Analyzing Audio Information To Determine Pitch And/Or Fractional Chirp Rate
Application:
13/205,455 →
Publication:
US 2013/0041489
System and Method for Tracking Sound Pitch Across an Audio Signal
Systems and Methods for Reconstructing an Audio Signal from Transformed Audio Information
Systems and Methods for Segmenting and/or Classifying an Audio Signal from Transformed Audio Information
System and Method for Tracking Sound Pitch Across an Audio Signal Using Harmonic Envelope
System and Method of Processing a Sound Signal Including Transforming the Sound Signal into a Frequency-Chirp Domain
Neural Processing Engine and Architecture Using the Same
Smart Memory
Systems and Methods for Packet Routing
I/O Data Interface for Packet Processors
Patent:
8,848,726 →
Application:
13/749,558 →
Identifying Speech Portions of a Sound Model Using Various Statistics Thereof
Patent:
9,058,820 →
Application:
13/899,264 →
Voice Enhancement and/or Speech Features Extraction on Noisy Audio Signals Using Successively Refined Transforms
Patent:
9,484,044 →
Application:
13/944,750 →
Reducing Octave Errors During Pitch Determination for Noisy Audio Signals
Patent:
9,530,434 →
Application:
13/945,731 →
Providing Sound Models of an Input Signal Using Continuous and/or Linear Fitting
Patent:
9,208,794 →
Application:
13/961,811 →
Neural Processing Engine and Architecture Using the Same
Patent:
10,083,394 →
Application:
14/020,660 →
System and Method of Processing a Sound Signal Including Transforming the Sound Signal into a Frequency-Chirp Domain
System and Method for Tracking Sound Pitch Across an Audio Signal Using Harmonic Envelope
Neural Processing Unit
Systems and Methods for Implementing a Platform for Processing Streams of Information
Application:
14/290,876 →
Publication:
US 2015/0350304
System and Method for Processing Sound Signals Implementing a Spectral Motion Transform
System and Methods for Personal Identification Number Authentication and Verification
Systems and Methods for Segmenting and/or Classifying an Audio Signal from Transformed Audio Information
I/O Data Interface for Packet Processors
Patent:
9,614,785 →
Application:
14/500,694 →
Systems and Methods for Estimating Pitch in Audio Signals Based on Symmetry Characteristics Independent of Harmonic Amplitudes
Patent:
9,396,740 →
Application:
14/502,844 →
Systems and Methods for Reconstructing an Audio Signal from Transformed Audio Information
Systems and Methods for Reconstructing an Audio Signal from Transformed Audio Information
Uniform System Wide Addressing for a Computing System
Mapping Processes to Processors in a Network on a Chip Computing System
Application:
14/608,505 →
Publication:
US 2016/0224379
Memory Controller for a Network on a Chip Device
Topology Discovery in a Computing System
Clustering of Audio Files Using Graphs
Access Code Obfuscation Using Speech Input
Performing Read Operations in Network on a Chip Architecture
Performing Write Operations In A Network On A Chip Device
Estimation of Noise Characteristics
Register Communication in a Network-on-a-Chip Architecture
Application:
14/921,377 →
Publication:
US 2017/0116154
Synchronization in a Multi-Processor Computing System
Application:
14/937,437 →
Publication:
US 2016/0224398
Writing to Contiguous Memory Addresses in a Network on a Chip Architecture
Multiple Operation Interface to Shared Coprocessor
Application:
14/946,054 →
Publication:
US 2017/0147345
Multiple Processor Access to Shared Program Memory
Application:
14/950,807 →
Publication:
US 2017/0147513
Dma Engine for Transferring Data in a Network-on-a-Chip Processor
Microprocessor Including Permutation Instructions
Application:
14/962,649 →
Publication:
US 2017/0161069
Estimating Pitch Using Symmetry Characteristics
Determining Features of Harmonic Signals
Estimating Fractional Chirp Rate with Multiple Frequency Representations
Estimating Pitch Using Peak-to-Peak Distances
Classifying Signals Using Feature Trajectories
Application:
15/000,135 →
Publication:
US 2017/0206904
Determining an Operation State Within a Computing System with Multi-Core Processing Devices
Application:
15/010,091 →
Publication:
US 2017/0220520
Harmonic Feature Processing for Reducing Noise
Data Routing and Buffering in a Processing System
Memory-Attached Computing Resource in Network on a Chip Architecture to Perform Calculations on Data Stored on Memory External to the Chip
Generating Models for Text-Dependent Speaker Verification
Application:
15/045,014 →
Publication:
US 2017/0236520
Synchronization in a Multi-Processor Computing System
Low-Latency Network Interface
Chained Packet Sequences in a Network on a Chip Architecture
Asynchronous Interface For Communications Between Computing Resources That Are In Different Clock Domains
Application:
15/098,257 →
Publication:
US 2017/0302430
Systems and Methods for Packet Routing
Estimating Clean Speech Features Using Manifold Modeling
Application:
15/140,081 →
Publication:
US 2017/0316790
Distributed Contiguous Reads in a Network on a Chip Architecture
Compute Unit Including Thread Dispatcher and Event Register and Method of Operating Same to Enable Communication
Application:
15/157,942 →
Publication:
US 2017/0337084
Content Addressable Memory (Cam) Implemented Tuple Spaces
Network on a Chip with Task Distribution Between Processing Elements
Application:
15/173,017 →
Publication:
US 2017/0351555
Performing a Synchronization Operation on an Electronic Device
Application:
15/177,068 →
Publication:
US 2017/0357705
Classifying Signals Using Correlations of Segments
Patent:
10,235,993 →
Application:
15/181,868 →
Encoding for Frameless Packet Transmissions
Application Domain Security
Application:
15/200,976 →
Publication:
US 2018/0006938
Arbitrating Access to a Resource That Is Shared by Multiple Processors
Application:
15/226,384 →
Publication:
US 2018/0039518
Router Path Selection and Creation in a Single Clock Cycle
Network Processor Inter-Device Packet Source ID Tagging for Domain Security
Application:
15/232,629 →
Publication:
US 2018/0048562
Flow Control Through Packet Router
Packet Router Buffer Management
Dedicated Fifos in a Multiprocessor System
Application:
15/276,232 →
Publication:
US 2018/0088904
Disjointed Virtual Memory Scheme with Block Bypass
Memory Controller for a Network on a Chip Device
Segmenting Utterances Within Speech
Application:
15/372,205 →
Publication:
US 2017/0294184
Affinity Data Collection in a Computing System
Harmonic Feature Processing for Reducing Noise
Estimating Pitch of Harmonic Signals
Classifying Signals Using Mutual Information
Application:
15/480,113 →
Publication:
US 2017/0294192
Segmentation Using Prior Distributions
Application:
15/481,403 →
Publication:
US 2017/0294185
Machine Learning Aggregation
Application:
15/498,201 →
Publication:
US 2017/0316345
Inclusion Monitors
Exclusion Monitors
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 16, 2006
From: EDELMAN, GERALD M.; KRICHMAR, JEFFREY L.; NITZ, DOUGLAS A.
To: NEUROSCIENCES RESEARCH FOUNDATION, INC.
Reel/Frame 017300/0533 →
Assignment of Assignor's Interest
Feb 16, 2006
From: SETH, ANIL K.; MCKINSTRY, JEFFREY L.; EDELMAN, GERALD M.; KRICHMAR, JEFFREY L.
To: NEUROSCIENCES RESEARCH FOUNDATION, INC.
Reel/Frame 017269/0583 →
Assignment of Assignor's Interest
Aug 7, 2006
From: SNOOK, JAMES A.; SCHERMERHORN, RICHARD W.
To: NEUROSCIENCES RESEARCH FOUNDATION, INC.
Reel/Frame 018067/0945 →
Assignment of Assignor's Interest
Oct 25, 2006
From: SNOOK, JAMES A.; HUTSON, DONALD B.; KRICHMAR, JEFFREY L.
To: NEUROSCIENCES RESEARCH FOUNDATION, INC.
Reel/Frame 018437/0132 →
Assignment of Assignor's Interest
Nov 18, 2009
From: MOORE, DOUGLAS A.; TSUKIDA, KRISTI H.; ANG, PAULO B.
To: THE INTELLISIS CORPORATION
Reel/Frame 023539/0654 →
Assignment of Assignor's Interest
Jul 15, 2010
From: LEWI, JEREMY W.
To: THE INTELLISIS CORPORATION
Reel/Frame 024690/0702 →
Assignment of Assignor's Interest
Aug 20, 2010
From: MOORE, DOUGLAS A.
To: THE INTELLISIS CORPORATION
Reel/Frame 024867/0497 →
Assignment of Assignor's Interest
Sep 16, 2010
From: MOORE, DOUGLAS A.
To: THE INTELLISIS CORPORATION
Reel/Frame 024996/0751 →
Assignment of Assignor's Interest
Jan 21, 2011
From: PALMER, DOUGLAS A.; FLOREA, MICHAEL
To: REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE
Reel/Frame 025689/0668 →
Assignment of Assignor's Interest
Jan 24, 2011
From: MOORE, DOUGLAS A.
To: THE INTELLISIS CORPORATION
Reel/Frame 025684/0675 →
Assignment of Assignor's Interest
Dec 6, 2011
From: BRADLEY, DAVID C.; FISHER, NICHOLAS K.; HILTON, ROBERT N.; GATEAU, RODNEY
To: THE INTELLISIS CORPORATION
Reel/Frame 027333/0986 →
Assignment of Assignor's Interest
Dec 6, 2011
From: MA, JIYONG
To: THE INTELLISIS CORPORATION
Reel/Frame 027339/0195 →
Assignment of Assignor's Interest
Dec 7, 2011
From: BRADLEY, DAVID C.; GOLDIN, DANIEL S.; HILTON, ROBERT N.; FISHER, NICHOLAS K.
To: THE INTELLISIS CORPORATION
Reel/Frame 027348/0848 →
Assignment of Assignor's Interest
Dec 8, 2011
From: MONRAZ, XAVIER; LEWI, JEREMY M.
To: THE INTELLISIS CORPORATION
Reel/Frame 027352/0020 →
Assignment of Assignor's Interest
Dec 9, 2011
From: BRADLEY, DAVID C.; GOLDIN, DANIEL S.; HILTON, ROBERT N.; FISHER, NICHOLAS K.
To: THE INTELLISIS CORPORATION
Reel/Frame 027369/0679 →
Assignment of Assignor's Interest
Dec 12, 2011
From: WIEWIORA, ERIC
To: THE INTELLISIS CORPORATION
Reel/Frame 027364/0761 →
Assignment of Assignor's Interest
Dec 12, 2011
From: HALEVY, SHALOM; MOORE, DOUGLAS A.
To: THE INTELLISIS CORPORATION
Reel/Frame 027367/0322 →
Assignment of Assignor's Interest
Dec 13, 2011
From: BRADLEY, DAVID C.; GOLDIN, DANIEL S.; GATEAU, RODNEY; FISHER, NICHOLAS K.
To: THE INTELLISIS CORPORATION
Reel/Frame 027378/0458 →
Corrective Assignment to Correct the Inventor's Middle Initial Previously Recorded on Reel 024690 Frame 0702. Assignor(S) Hereby Confirms the Assignment.
Apr 16, 2012
From: LEWI, JEREMY M.
To: THE INTELLISIS CORPORATION
Reel/Frame 028052/0135 →
Change of Name
Apr 28, 2016
From: THE INTELLISIS CORPORATION
To: KNUEDGE INCORPORATED
Reel/Frame 038546/0192 →
Change of Name
Jun 9, 2016
From: THE INTELLISIS CORPORATION
To: KNUEDGE INCORPORATED
Reel/Frame 038926/0223 →
Security Interest
Nov 11, 2016
From: KNUEDGE INCORPORATED
To: XL INNOVATE FUND, L.P.
Reel/Frame 040601/0917 →
Change of Name
Feb 14, 2017
From: THE INTELLISIS CORPORATION
To: KNUEDGE INCORPORATED
Reel/Frame 041715/0745 →
Assignment of Assignor's Interest
Sep 26, 2018
From: KNUEDGE, INC.
To: FRIDAY HARBOR LLC
Reel/Frame 047156/0582 →
Assignment of Assignor's Interest
Jan 11, 2019
From: KNUEDGE, INC.
To: FRIDAY HARBOR LLC
Reel/Frame 047968/0898 →