MULTIPLE PROCESSOR ACCESS TO SHARED PROGRAM MEMORY
A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data from the same memory locations. Data from that memory location is then accessed and sent to the requesting processors so that the data arrives at about the same time to each processor, for example, during the same clock cycle. Such distribution is made possible using a configuration such as a shared data bus with corresponding valid bits for each register or using a multicaster and separate data busses for each processor.
1 . A semiconductor chip comprising:
a shared memory storing instructions operable by a processor core;
a plurality of processing elements, each processing element comprising:
a processor core,
a data input, and
an address output;
at least one arbitration component connected to:
the address output of each of the plurality of processing elements, and
a plurality of output valid bit lines, each output valid bit line corresponding to one of the plurality of processing elements,
wherein the at least one arbitration component is configured to:
compare the respective address outputs to determine matching requested address locations output from the plurality of processing elements,
output a memory address to the shared memory, and
set output valid bit lines for the respective processing elements that requested data from the memory address; and
at least one data bus connecting an output of the shared memory to the data input of each of the plurality of processing elements.
2 . The semiconductor chip of claim 1 , wherein the at least one arbitration component is further configured to:
receive a first address from a first address output of a first processing element of the plurality of processing elements;
receive the first address from a second address output of a second processing element of the plurality of processing elements;
determine that the first address output and second address output include the same first address;
send the first address to the shared memory; and
set a first output valid bit line corresponding to the first processing element and set the second output valid bit line corresponding to the second processing element.
3 . The semiconductor chip of claim 2 , wherein:
the at least one data bus is a shared data bus;
each processing element is connected to a respective output valid bit line; and
the first output valid bit line and second output valid bit line are set at a time corresponding to a time at which the shared memory outputs data corresponding to the first address to the shared data bus.
4 . The semiconductor chip of claim 2 , wherein the at least one arbitration component comprises a multicaster and the multicaster is:
connected to the output valid bit lines;
connected to the output of the shared memory; and
connected to a plurality of data bus lines, each data bus line connected to a data input of a processing element of the plurality of processing elements,
wherein the multicaster is configured to:
in response to the first output valid bit line being set, output first data corresponding to the output of the shared memory to a first data bus line, the first data bus line connected to the first processing element and corresponding to the first output valid bit line; and
in response to the second output valid bit line being set, output the first data to a second data bus line, the second data bus line connected to the second processing element and corresponding to the second output valid bit line.
5 . The semiconductor chip of claim 4 , wherein the outputting the first data onto the first data bus line and outputting the first data onto the second data bus line occurs within a same clock cycle.
6 . The semiconductor chip of claim 1 , wherein the at least one arbitration component is further configured to:
in response to the first output valid bit line being set, set an acknowledgement bit connected to the first processing element; and
in response to the second output valid bit line being set, set an acknowledgement bit connected to the second processing element.
7 . The semiconductor chip of claim 1 , further comprising an address line connecting an output of the shared memory to each of the plurality of processing elements.
8 . A method comprising:
loading a first memory address from a first processing element;
loading a second memory address from a second processing element;
determining that the first memory address and second memory address are the same;
sending the first memory address to a memory component;
outputting, from the memory component, first data stored at a location within the memory component corresponding to the first memory address; and
sending, within a first clock cycle, the first data to the first processing element and to the second processing element.
9 . The method of claim 8 , further comprising, prior to sending the first data:
setting a first output valid bit line corresponding to the first processing element; and
setting a second output valid bit line corresponding to the second processing element.
10 . The method of claim 9 , further comprising:
based on the first output valid bit line being set, sending the data to the first processing element using a first data bus; and
based on the second output valid bit line being set, sending the data to the second processing element using a second data bus.
11 . The method of claim 8 , wherein the first data is sent on a shared data bus to the first processing element and to the second processing element.
12 . The method of claim 8 , further comprising:
in response to the first output valid bit line being set, set an acknowledgement bit connected to the first processing element; and
in response to the second output valid bit line being set, set an acknowledgement bit connected to the second processing element.
13 . The method of claim 8 , wherein the loading and determining are performed by at least one arbitration component.
14 . The method of claim 8 , further comprising sending, to the first processing element and to the second processing element, the first memory address at a same time as the first data.
15 . A system configured for:
loading a first memory address from a first processing element;
loading a second memory address from a second processing element;
determining that the first memory address and second memory address are the same;
sending the first memory address to a memory component;
outputting, from the memory component, first data stored at a location within the memory component corresponding to the first memory address; and
sending, within a first clock cycle, the first data to the first processing element and to the second processing element.
16 . The system of claim 15 , further configured for, prior to sending the first data:
setting a first output valid bit line corresponding to the first processing element; and
setting a second output valid bit line corresponding to the second processing element.
17 . The system of claim 16 , further configured for:
based on the first output valid bit line being set, sending the data to the first processing element using a first data bus; and
based on the second output valid bit line being set, sending the data to the second processing element using a second data bus.
18 . The system of claim 15 , wherein the first data is sent on a shared data bus to the first processing element and to the second processing element.
19 . The system of claim 15 , configured for:
in response to the first output valid bit line being set, set an acknowledgement bit connected to the first processing element; and
in response to the second output valid bit line being set, set an acknowledgement bit connected to the second processing element.
20 . The system of claim 15 , wherein the loading and determining are performed by at least one arbitration component.
21 . The system of claim 15 , configured for sending, to the first processing element and to the second processing element, the first memory address at a same time as the first data.