Data routing and buffering in a processing system
In a computing system where an incoming packet can be written directly into one or more local registers of a processing unit, a packet interface routes packets arriving at a computing system to the local registers of the processing unit or to a memory shared by multiple processing units. The shared memory includes a portion configured as a first-in, first-out (FIFO) buffer for storing packets arriving for the processing unit when its local registers are full. The stored packets are then delivered to the processing unit's one or more registers when the registers become available.
1. A system comprising:
packet interface circuitry;
a first processing unit comprising a processor core configured to process data packets and at least one register configured to store a data packet received from the packet interface circuitry to be processed by the processor core; and
a memory device accessible to a plurality of processing units including the first processing unit, the memory device comprising a portion configured to store data packets received from the packet interface circuitry to be processed by the processor core of the first processing unit;
wherein the packet interface circuitry is configured to perform operations including:
receive a data packet to be processed by the processor core;
determine whether the at least one register of the first processing unit contains valid data by checking a valid flag corresponding to the at least one register;
determine whether the memory device portion contains valid data;
in response to determining (I) that the valid flag corresponding to the at least one register is clear, and (II) that the memory device portion does not contain valid data,
(a) causing the received data packet to be stored in the at least one register and
(b) setting the valid flag corresponding to the at least one register;
in response to determining (I) that the valid flag corresponding to the at least one register is clear, and (II) that the memory device portion contains valid data,
(a) causing the received data packet to be stored in the memory device portion, or
(b) causing a data packet previously stored in the memory device portion to be transferred to the at least one register, and setting the valid flag corresponding to the at least one register; and
in response to determining that the valid flag is set, causing the received data packet to be stored in the memory device portion; and
wherein the first processing unit is configured to clear the valid flag corresponding to the at least one register after all data stored in the at least one register has been processed by the processor core of the first processing unit.
2. The system of claim 1 , wherein the memory device portion is configured as a first-in, first-out (FIFO) buffer.
3. The system of claim 1 , wherein a starting memory location and a size of the memory device portion is programmable.
4. The system of claim 1 , wherein the memory device comprises a plurality of portions including the memory device portion, each of the plurality of portions associated with a corresponding processing unit of the plurality of processing units, and each of the plurality of portions being configured to store data packets received from the packet interface circuitry to be processed by a processor core of the associated processing unit.
5. The system of claim 1 , wherein the packet interface circuitry configured to determine whether the memory device portion contains valid data comprises:
circuitry configured to check a valid flag corresponding to the memory device portion.
6. The system of claim 5 , wherein the packet interface circuitry is configured to perform operations further comprising:
set the valid flag corresponding to the memory device portion when causing a received data packet to be stored in the memory device portion; and
clear the valid flag corresponding to the memory device portion when all data packets previously stored in the memory device portion have been transferred to the at least one register.
7. The system of claim 1 wherein the packet interface circuitry configured to perform operations is configured at least in part through software.
8. A method comprising:
receiving, by packet interface circuitry, a data packet to be processed by a processor core of a first processing unit, the processor core configured to process data packets stored by at least one register of the first processing unit;
determining whether the at least one register of the first processing unit contains valid data by checking, by the packet interface circuitry, a valid flag corresponding to the at least one register;
determining, by the packet interface circuitry, whether a memory device portion, accessible by a plurality of processing units including the first processing unit, contains valid data;
in response to determining (I) that the valid flag corresponding to the at least one register is clear, and (II) that the memory device portion does not contain valid data,
(a) causing, by the packet interface circuitry, the received data packet to be stored in the at least one register, and
(b) setting, by the packet interface circuitry, the valid flag corresponding to the at least one register;
in response to determining (I) that the valid flag corresponding to the at least one register is clear, and (II) that the memory device portion contains valid data,
(a) causing, by the packet interface circuitry, the received data packet to be stored in the memory device portion, or
(b) causing a data packet previously stored in the memory device portion to be transferred to the at least one register, and setting, by the packet interface circuitry, the valid flag corresponding to the at least one register; and
in response to determining that the valid flag is set, causing the received data packet to be stored in the memory device portion; and
clearing, by the first processing unit, the valid flag corresponding to the at least one register after all data stored in the at least one register has been processed by the processor core of the first processing unit.
9. The method of claim 8 , wherein the memory device portion is configured as a first-in, first-out (FIFO) buffer.
10. The method of claim 8 , wherein a starting memory location and a size of the memory device portion is programmable.
11. The method of claim 8 , wherein the memory device comprises a plurality of portions including the memory device portion, each of the plurality of portions associated with a corresponding processing unit of the plurality of processing units, and each of the plurality of portions being configured to store data packets to be processed by a processor core of the associated processing unit.
12. The method of claim 8 , wherein determining whether the memory device portion contains valid data comprises checking, by the packet interface circuitry, a valid flag corresponding to the memory device portion.
13. The method of claim 12 , further comprising:
setting, by the packet interface circuitry, the valid flag corresponding to the memory device portion when causing a received data packet to be stored in the memory device portion; and
clearing, by the packet interface circuitry, the valid flag corresponding to the memory device portion when all data packets previously stored in the memory device portion have been transferred to the at least one register.
14. The method of claim 8 wherein the method is performed at least in part through software.