Synchronization in a multi-processor computing system

1. A system comprising a host device, a plurality of processing devices, a first-level sync controller, a first second-level sync controller, and a second second-level sync controller wherein:

the host device is configured to transmit instructions and data to the plurality of processing devices and to transmit sync information to the first-level sync controller, the first second-level sync controller, and the second second-level sync controller;

the first-level sync controller is configured to receive a first portion of the sync information, wherein the first portion (i) identifies a first sync process, (ii) indicates that the first-level sync controller is a master controller of the first sync process; and (iii) identifies a group of second-level sync controllers that are executing the first sync process, the group of second-level controllers including the first second-level sync controller and the second second-level sync controller;

the first second-level sync controller is configured to receive a second portion of the sync information, wherein the second portion (i) identifies the first sync process and (ii) identifies a first group of processing devices that are executing the first sync process;

the second second-level sync controller is configured to receive a third portion of the sync information, wherein the third portion (i) identifies the first sync process and (ii) identifies a second group of processing devices that are executing the first sync process;

a first processing device of the plurality of processing devices is configured to execute a first plurality of instructions and transmit a first sync indication to the first second-level controller;

a second processing device of the plurality of processing devices is configured to execute a second plurality of instructions and transmit a second sync indication to the second second-level controller;

the first second-level controller is configured to:

receive the first sync indication from the first processing device;

store an indication, associated with the first sync process, that the first sync indication was received from the first processing device;

determine that a sync indication has been received from all processing devices of the first group of processing devices;

transmit a third sync indication to the first-level controller;

the second second-level controller is configured to:

receive the second sync indication from the second processing device;

store an indication, associated with the first sync process, that the second sync indication was received from the second processing device;

determine that a sync indication has been received from all processing devices of the second group of processing devices;

transmit a fourth sync indication to the first-level controller;

the first-level controller is configured to:

receive the third sync indication;

store an indication, associated with the first sync process, that the third sync indication was received from the first second-level controller;

receive the fourth sync indication;

store an indication, associated with the first sync process, that the fourth sync indication was received from the second second-level controller;

determine that a sync indication has been received from all second-level controllers in the group of second-level controllers; and

transmit a notification that the first sync process is complete.

2. The system of claim 1 , wherein the first-level controller is configured to send the notification to the host device.

3. The system of claim 1 , wherein:

the first-level controller is further configured to transmit a first notification to the first second-level controller and to transmit a second notification to the second second-level controller; and

the first second-level controller is configured to send a third notification to the first processing device.

4. The system of claim 3 , wherein the first processing device is configured to execute instructions in response to receiving the third notification from the first second-level controller.

5. The system of claim 1 , wherein the host device transmits the sync information indirectly to the first-level sync controller, the first second-level sync controller, and the second second-level sync controller.

6. The system of claim 3 , wherein:

the first-level controller is further configured to:

determine a time for transmission of notifications to processing devices;

include the time in the first notification; and

the first second-level controller is configured to send the third notification at the determined time.

7. The system of claim 1 , wherein the first processor is configured to send the first sync indication by changing a state of an output pin of the first processing device.

8. A method, implemented by a first sync controller, comprising:

receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device;

receiving a first sync indication from the first processing device;

storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device;

determining that a sync indication has been received from all components of the first group of components; and

transmitting a second sync indication to a second sync controller.

9. The method of claim 8 , further comprising:

receiving from the second sync controller a first notification that the first sync process is complete; and

transmitting a second notification to the first processing device that the first sync process is complete.

10. The method of claim 8 , wherein storing the indication comprises storing a value in a register.

11. The method of claim 8 , wherein transmitting the second sync indication to the second controller comprises using a serial connection.

12. The method of claim 8 , wherein receiving the first sync indication comprises reading a state of an output pin of the first processing device.

13. The method of claim 8 , wherein the second sync controller is a master controller for the first sync process.

14. The method of claim 8 , wherein the sync information (i) identifies a second sync process, (ii) indicates that the first sync controller is a master controller of the second sync process, and (iii) identifies a second group of components executing the second sync process.

15. The method of claim 8 , wherein transmitting the second sync indication to the second sync controller comprises sending a packet.

16. The method of claim 8 , wherein the group of components comprises a buffer and wherein the method further comprises receiving a third sync indication from the buffer.

17. A processing device comprising:

a plurality of processor cores;

a first input port for receiving data;

a first output port for transmitting data;

a second input port for receiving sync indications;

a second output port for transmitting sync indications;

at least one memory comprising executable instructions that configure the processing device to perform operations including the following:

receive first data via the first input port;

process the first data with at least one processor core to generate second data;

transmit the second data via the first output port;

determine that criteria have been satisfied for sending a sync indication;

transmit a sync indication to a sync controller via the second output port in response to determining that the criteria have been satisfied;

receive a sync notification via the second input port; and

perform subsequent processing in response to receiving the sync notification.

18. The processing device of claim 17 , wherein the first input port comprises a serial connection, and the at least one memory comprising executable instructions that configure the processing device to receive first data via the first input port comprises:

the at least one memory comprising executable instructions that configure the processing device to receive packets comprising the first data via the serial connection.

19. The processing device of claim 17 , wherein the first output port comprises a serial connection, and the at least one memory comprising executable instructions that configure the processing device to transmit the second data via the first output port comprises:

the at least one memory comprising executable instructions that configure the processing device to transmit packets comprising the second data via the serial connection.

20. The processing device of claim 17 , wherein the second output port comprises a wire connection, and the at least one memory comprising executable instructions that configure the processing device to transmit the sync indication to the sync controller via the second output port comprises:

the at least one memory comprising executable instructions that configure the processing device to assert a signal that is transmitted over the wire connection via the second output port.

21. The processing device of claim 17 , wherein the second input port comprises a wire connection, and the at least one memory comprising executable instructions that configure the processing device to receive the sync notification via the second input port comprises:

the at least one memory comprising executable instructions that configure the processing device to receive an asserted signal transmitted over the wire connection via the second input port.