Content addressable memory (CAM) implemented tuple spaces
A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.
1. A multiprocessor integrated on a semiconductor chip, comprising:
a first processing element;
a second processing element; and
a content addressable memory (CAM) comprising a plurality of tuple spaces, wherein the CAM is configured to:
receive a read request from the first processing element, the read request including a first tag and an instruction to perform a read operation from a first tuple space of the plurality of tuple spaces, the first tuple space being associated with the first tag;
receive a write request from the second processing element, the write request including the first tag and an instruction to perform a write operation to the first tuple space;
write data associated with the write request to the first tuple space;
based at least in part on writing the data, set a first indicator associated with the first tuple space;
after writing the data, determine that the first indicator is set;
based at least in part on the first indicator being set, read the data from the first tuple space; and
send the data to the first processing element.
2. The multiprocessor integrated on a semiconductor chip of claim 1 , wherein:
the read request comprises the first tag; and
the CAM is further configured to determine whether the first tuple space is associated with the first tag prior to determining the first indicator is set.
3. The multiprocessor integrated on a semiconductor chip of claim 2 , wherein the CAM is further configured to:
clear, after the data is read, the first indicator associated with the first tuple space.
4. The multiprocessor integrated on a semiconductor chip of claim 2 , wherein the CAM is further configured to:
after receiving the read request and prior to writing the data, determine that the first indicator is not set; and
based on determining the first indicator is not set, stall the read request until the first indicator indicates that the second processing element has performed the write operation to the first tuple space.
5. The multiprocessor integrated on a semiconductor chip of claim 4 , wherein the first processing element is configured to remain idle until the first indicator indicates that the second processing element has performed the write operation to the first tuple space.
6. The multiprocessor integrated on a semiconductor chip of claim 1 , wherein the CAM is further configured to:
receive, from a third processing element, a write request associated with a second tag and second data; and
determine whether a second tuple space of the plurality of tuple spaces is associated with the second tag.
7. The multiprocessor integrated on a semiconductor chip of claim 6 , wherein the CAM is further configured to:
associate the second tag to the second tuple space when the second tuple space is not associated with the second tag; and
store the second data at the second tuple space.
8. The multiprocessor integrated on a semiconductor chip of claim 6 , wherein the CAM is further configured to block the write request when a second indicator indicates that a read operation has not been performed on the second tuple space.
9. The multiprocessor integrated on a semiconductor chip of claim 8 , wherein the third processing element is configured to remain idle until the second indicator indicates that a read operation has been performed on the second tuple space.
10. The multiprocessor integrated on a semiconductor chip of claim 1 , wherein, in response to the first indicator initially indicating that the second processing element has not performed the write operation, the CAM is configured to:
before determining that the first indicator is set, send a message to the first processing element that the first tuple space is not ready for reading;
receive a later request from the second processing element to write the data to the first tuple space;
write the data to the first tuple space; and
set the first indicator to indicate that the first tuple space is ready for reading.
11. A computer implemented method, the method comprising:
configuring, in a content addressable memory (CAM), a plurality of locations as a plurality of tuple spaces;
receiving, at the CAM, a read request from a first processing element, the read request including a first tag and an instruction to perform a read operation from a first tuple space of the plurality of tuple spaces, the first tuple space being associated with the first tag;
receiving, at the CAM, a write request from a second processing element, the write request including the first tag and an instruction to perform a write operation to the first tuple space;
writing, at the CAM, data associated with the write request to the first tuple space;
based at least in part on writing the data, setting a first indicator associated with the first tuple space;
after writing the data, determining that the first indicator is set;
based at least in part on the first indicator being set, reading, at the CAM, the data from the first tuple space; and
sending, from the CAM, the data to the first processing element.
12. The computer implemented method of claim 11 , wherein:
the read request comprises the first tag; and
the CAM is further configured to determine whether the first tuple space is associated with the first tag prior to determining the first indicator is set.
13. The computer implemented method of claim 12 , wherein the computer implemented method further comprises clearing, after the data is read, the first indicator associated with the first tuple space.
14. The computer implemented method of claim 12 , wherein the computer implemented method further comprises:
after receiving the read request and prior to writing the data, determining that the first indicator is not set; and
based on determining the first indicator is not set, stalling the read request when the first indicator indicates that the second processing element has not performed the write operation to the first tuple space.
15. The computer implemented method of claim 14 , wherein the first processing element is configured to remain idle until the first indicator indicates that the second processing element has performed the write operation to the first tuple space.
16. The computer implemented method of claim 11 , wherein the computer implemented method further comprises:
receiving, from a third processing element, a write request associated with a second tag and second data; and
determining whether a second tuple space of the plurality of tuple spaces is associated with the second tag.
17. The computer implemented method of claim 16 , wherein the computer implemented method further comprises:
associating the second tag to the second tuple space when the second tuple space is not associated with the second tag; and
storing the second data at the second tuple space.
18. The computer implemented method of claim 16 , wherein the computer implemented method further comprises blocking the write request when a second indicator indicates that a read operation has not been performed on the second tuple space.
19. The computer implemented method of claim 18 , wherein the third processing element is configured to remain idle until the second indicator indicates that a read operation has been performed on the second tuple space.
20. An apparatus integrated on a semiconductor chip, the apparatus comprising:
means for configuring a plurality of memory locations as a plurality of tuple spaces;
means for receiving a read request from a first processing element, the read request including a first tag and an instruction to perform a read operation from a first tuple space of the plurality of tuple spaces, the first tuple space being associated with the first tag;
means for receiving a write request from a second processing element, the write request including the first tag and an instruction to perform a write operation to the first tuple space;
means for writing data associated with the write request to the first tuple space;
means for, based at least in part on writing the data, setting a first indicator associated with the first tuple space;
means for, after writing the data, determining that the first indicator is set;
means for, based at least in part on the first indicator being set, reading the data from the first tuple space; and
means for sending the data to the first processing element.