Uniform back side exposure of through-silicon vias
Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.
1. A semiconductor device comprising:
a substrate having a front side, a plurality of circuit elements formed proximate the front side, and a back side opposite the front side;
a through-silicon via (TSV) extending at least between the front side and the back side, and having a first exposed surface proximate the back side;
a first dielectric material over the back side of the substrate;
a metallic dummy feature disposed over the first dielectric material and spaced laterally apart from the TSV such that the first dielectric material contacts a lower surface of the dummy feature, wherein the dummy feature includes a second exposed surface proximate the back side and substantially coplanar with the first exposed surface; and
a second dielectric material over the first dielectric material and laterally disposed between the TSV and the dummy feature such that the second dielectric material contacts a side surface of the dummy feature,
wherein the dummy feature has a chemical-mechanical planarization (CMP) removal rate that is lower than a CMP removal rate of the second dielectric material.
2. The semiconductor device of claim 1 , further comprising a second dummy feature between the first dummy feature and the TSV.
3. The semiconductor device of claim 1 , further comprising a second dummy feature, wherein the first and second dummy features are disposed on opposite sides of the TSV.
4. The semiconductor device of claim 1 wherein the substrate comprises a memory circuit.
5. The semiconductor device of claim 1 wherein the TSV comprises a conductive fill material, and the dummy feature comprises the same material.
6. The semiconductor device of claim 5 wherein the material comprises copper.
7. The semiconductor device of claim 1 wherein the dummy feature is not in electrical communication with any active components of the device.
8. The semiconductor device of claim 1 wherein the dummy feature does not penetrate the substrate.
9. The semiconductor device of claim 1 wherein the second dielectric material is substantially coplanar with the TSV and the dummy feature.
10. The semiconductor device of claim 1 , wherein the dummy feature is laterally spaced from the TSV by at least 20 microns.
11. The semiconductor device of claim 1 wherein a width of the dummy feature is less than a width of the TSV.
12. The semiconductor device of claim 1 wherein the dummy feature has a substantially circular cross-section.
13. The semiconductor device of claim 1 wherein the dummy feature is a line.
14. A method of manufacturing a semiconductor device, the method comprising:
forming a through-silicon via (TSV) in a substrate, the TSV including a conductive material extending through the substrate and projecting from a back side of the substrate;
forming a first dielectric material over the back side of the substrate;
forming a metallic dummy feature over the first dielectric material such that the first dielectric material contacts a lower surface of the dummy feature, the dummy feature laterally spaced apart from the TSV; and
forming a second dielectric material over the first dielectric material, the second dielectric material laterally disposed between the TSV and the dummy feature such that the second dielectric material contacts a side surface of the dummy feature,
wherein the dummy feature has a chemical-mechanical planarization (CMP) removal rate that is lower than a CMP removal rate of the second dielectric material.
15. The method of claim 14 wherein the second dielectric material substantially surrounds the dummy feature.
16. The method of claim 15 wherein the second dielectric material covers the dummy feature and the conductive material of the TSV.
17. The method of claim 14 , further comprising planarizing the back side such that an exposed surface of the dummy feature is substantially coplanar with an exposed surface of the conductive material of the TSV.
18. The method of claim 17 wherein the planarizing comprises using a chemical-mechanical planarization (CMP) process.
19. The method of claim 14 wherein forming the dummy feature comprises:
defining an opening in the second dielectric material over the back side of the substrate;
forming a seed material in the opening; and
plating a material in the opening to form the dummy feature.
20. The method of claim 19 wherein forming the seed material comprises forming the seed material over the second dielectric material, the method further comprising:
depositing a mask over the seed material, the mask patterned to expose portions of the seed material in the opening in the second dielectric material.
21. The method of claim 20 , further comprising:
removing the mask after forming the dummy feature; and
depositing an additional dielectric material over the second dielectric material and the dummy feature.
22. The method of claim 14 wherein the dummy feature comprises copper.