Large channel interconnects with through silicon vias (TSVs) and method for constructing the same

1. An electrical device comprising:

at least two active wafers at least one of which having at least one through silicon via wherein each of the at least one through silicon via is comprised of only one metal layer; and

a plurality of unitary electrical communication and spacer structures present between a set of adjacently stacked active wafers of the at least two active wafers, the unitary electrical communication and spacer structure comprising an electrically conductive material core that is the only metal layer of the unitary electrical communication and spacer structure, and providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer, a semiconductor material sidewalls having a substantially conformal width that is substantially the same for each of the plurality of unitary electrical communication and spacer structures that is encircling the electrically conductive material core, and a solid dielectric layer having a substantially same width as a diameter of the electrically conductive material core between and in direct contact with both the substrate material outer layer and the electrically conductive material core, the at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the semiconductor material sidewalls of adjacent unitary electrical communication and spacer structures in said plurality of unitary electrical communication and spacer structures, the plurality of unitary electrical communication and spacers structures include three or more unitary electrical communication and spacers structures having one of said coolant passages between each adjacent unitary electrical communication structures of the three or more unitary electrical communication structures to provide three or more coolant passages separated by a same pitch, wherein the plurality of unitary electrical communication and spacer structures further comprise a dielectric epoxy based sealant between the substrate material outer layer of the unitary electrical communication and spacer structure and the set of adjacently stacked active wafers that the unitary electrical communication and spacer structure is engaged to.

2. The electrical device of claim 1 , wherein at least one of the at least two active wafers including semiconductor devices, memory devices, passive electrical devices, and a combination thereof.

3. The electrical device of claim 1 , wherein at least one of the at least two active wafers comprise a semiconductor substrate comprised of a material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor materials and a combination thereof.

4. The electrical device of claim 1 , wherein the electrically conductive material core is a metal selected from the group consisting of W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloys thereof.

5. The electrical device of claim 1 , wherein the width of each of the coolant passages ranges from 100 microns to 200 microns, and the height of each of the coolant passages ranges from 100 microns to 500 microns.

6. The electrical device of claim 1 , wherein the plurality unitary electrical communication and spacer structure comprises a column containing a plurality of unitary electrical communication and spacer structures.

7. An electrical device comprising:

at least two active wafers at least one of which having at least one through silicon via wherein each of the at least one through silicon via is comprised of only one metal layer; and

a plurality of unitary electrical communication and spacer structures present between a set of adjacently stacked active wafers of the at least two active wafers, the unitary electrical communication and spacer structure comprising an electrically conductive material core that is the only metal layer of the unitary electrical communication and spacer structure, and providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers, a semiconductor material sidewalls having a substantially conformal width encircling the electrically conductive material core, and a solid dielectric layer having a substantially same width as a diameter of the electrically conductive material core between and in direct contact with both the substrate material outer layer and the electrically conductive material core, the plurality unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers through a solder joint, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the semiconductor material sidewalls of adjacent unitary electrical communication and spacer structures in said plurality of unitary electrical communication and spacer structures, the plurality of unitary electrical communication and spacers structures include three or more unitary electrical communication and spacers structures having a coolant passage between each adjacent unitary electrical communication structures of the three or more unitary electrical communication structures to provide three of more of said coolant passages separated by a same pitch, wherein the plurality of unitary electrical communication and spacer structures further comprise a dielectric epoxy based sealant between the substrate material outer layer of the unitary electrical communication and spacer structure and the set of adjacently stacked active wafers that the unitary electrical communication and spacer structure is engaged to.