Programmable buffer system
View Patent ↗A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.
1. A programmable buffer system comprising:
a plurality of programmable resources, each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer;
configuration information registers that specify:
whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and
which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.
2. The programmable buffer system of claim 1 , further comprising:
a timer resource that provides the plurality of timer signals.
3. The programmable buffer system of claim 1 , wherein when one of the plurality of programmable resources is configured as the logic block:
a logic multiplexer is configured to receive input from the buffer, a control input from the input multiplexer, and to provide an input to the output multiplexer, and
an output of the output multiplexer is provided to the input multiplexer.
4. The programmable buffer system of claim 3 , wherein, when the one of the plurality of programmable resources is configured as the logic block:
the fields of the buffer store output values for combinations of input values.
5. The programmable buffer system of claim 1 , wherein:
at least two of the programmable resources are coupled to one another to implement the one of the group consisting of: the logic block, the shift register, and the state record.
6. The programmable buffer system of claim 1 , wherein:
a first of the programmable resources is coupled to a second of the programmable resources, and each of the first and second programmable resources are configured as a different one of the group consisting of: the logic block, the shift register, and the state record.
7. The programmable buffer system of claim 1 , wherein, when one of the plurality of programmable resources is configured as the shift register;
one of the plurality of timer signals corresponds to an input/output protocol is provided to the buffer,
the input multiplexer is coupled to provide input to the buffer,
the buffer is configured to provide an input to the output multiplexer, and
an output of the output multiplexer is provided as an input to the input multiplexer.
8. The programmable buffer system of claim 7 , wherein, when the one of the plurality of programmable resources is configured as the shift register;
fields of the buffer store input/output data in a format specified by input/output protocol.
9. The programmable buffer system of claim 1 , further comprising:
state pointer logic;
wherein when more than one of the plurality of programmable resources are configured as the state record, each of the more than one of the plurality of programmable resources includes a first state multiplexer and an output multiplexer, and
in each of the more than one of the plurality of programmable resources:
the buffer provides an output indicating next states of a state pointer for one of the more than one of the plurality of programmable resources to the first state multiplexer and output data to the output multiplexer, and
the first state multiplexer receives a control input from the input multiplexer and provides a first output indicating one of the next states for the one of the more than one of the plurality of programmable resources to the state pointer logic.
10. The programmable buffer system of claim 9 wherein:
the state pointer logic includes a second state multiplexer, a state pointer register, and a timer multiplexer,
the second state multiplexer receives a second input indicating next states from other of the more than one of the plurality of programmable resources and a control input to select between the next state of the one of the more than one of the plurality of programmable resources and the next states of the other of the more than one of the plurality of programmable resources, and
the state pointer register stores an output from the second state multiplexer when a clock trigger signal is received from the timer multiplexer.
11. A method of operating a programmable buffer system comprising:
providing configuration information in a configuration register associated with the programmable buffer system for two or more sets of programmable resources, wherein for each of the two or more sets of programmable resources, the configuration information includes:
an indicator of whether one of the two or more sets of programmable resources is to be configured as a logic block, a state record, or a shift register; and
which of a plurality of timer signals to use for the one of the two or more sets of programmable resources, wherein, before any of the configuration information is used to configure the one of two or more sets of programmable resources, each of the two or more sets of programmable resources includes a buffer, an input multiplexer, and an output multiplexer.
12. The method of claim 11 further comprising:
when the one of the two or more sets of programmable resources is configured as the logic block:
configuring a logic multiplexer to receive an input from the buffer and a control input from the input multiplexer and to provide an input to the output multiplexer, and
providing an output of the output multiplexer to the input multiplexer.
13. The method of claim 12 further comprising:
when the one of the two or more sets of programmable resources is configured as the logic block, storing output values for combinations of input values in entries of the buffer.
14. The method of claim 11 , further comprising:
when the one of the two or more sets of programmable resources is configured as the shift register:
providing one of the plurality of timer signals corresponding to an input/output protocol to the buffer,
coupling the input multiplexer to provide input to the buffer,
coupling the buffer to provide an input to the output multiplexer, and
providing an output of the output multiplexer as an input to the input multiplexer.
15. The method of claim 14 further comprising:
when more than the one of the two or more sets of programmable resources are configured as the shift register, entries of the buffer store input/output data in a format specified by input/output protocol.
16. The method of claim 11 further comprising:
when more than one of the two or more sets of programmable resources are configured as the state record, each of the more than the one of the two or more sets of programmable resources includes a first state multiplexer and an output multiplexer, and
in each of the more than one of the two or more sets of programmable resources configured as the state record:
configuring the buffer to provide an output indicating next states of a state pointer to the first state multiplexer and output data to the output multiplexer circuit, and
configuring the first state multiplexer to receive a control input from the input multiplexer and provide a first output indicating one of the next states of a corresponding one of the more than one of the two or more sets of programmable resources configured as the state record to state pointer logic.
17. The method of claim 16 , wherein the state pointer logic includes a second multiplexer, a state pointer register, and a timer multiplexer, the method further comprising:
receiving in the second state multiplexer a second input indicating next states from other of the two or more sets of programmable resources and a control input to select between the next state of the corresponding one of the two or more sets of programmable resources and the next states of the other of the two or more sets of programmable resources, and
storing in the state pointer register an output from the second state multiplexer when a clock trigger signal is received from the timer multiplexer.
18. A programmable buffer system comprising:
in an unconfigured state:
a plurality of programmable resources;
a plurality of input multiplexers coupled to the plurality of programmable resources; and
a plurality of output multiplexers coupled to the plurality of programmable resources; and
a user configuration register including information to configure the plurality of programmable resources as one or more logic blocks, one or more state records, one or more shift registers, or a combination of two or more of a group consisting of a logic block, a state record, and a shift register, wherein the user configuration register further includes information that specifies which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.
19. The programmable buffer system of claim 18 , further comprising:
a timer resource that provides the plurality of timer signals.