IP Library Granted Patent US 9,691,777
Granted Patent B2
US 9,691,777 · App. 14/614,586 · Granted Jun 27, 2017

Non-volatile semiconductor memory device

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Quick Facts
Patent No.
US 9,691,777
App. No.
14/614,586
Granted
Jun 27, 2017
Kind
B2
Abstract

A semiconductor memory device includes a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, a first conductive film disposed on the first insulating film, a second insulating film disposed on the first conductive film, a second conductive film disposed on the second insulating film, a first electrode disposed on the first conductive film through an opening formed in the second conductive film and the second insulating film, and having a first width, a second electrode that is formed on the first electrode and having a second width, and a wiring layer that is formed on the second electrode. A first width of the first electrode is wider than a second width of the second electrode.

Claims (51)

1. A semiconductor memory device comprising:

a semiconductor substrate;

a first insulating film disposed on the semiconductor substrate;

a first conductive film disposed on the first insulating film;

a second insulating film disposed on the first conductive film;

a second conductive film disposed on the second insulating film;

a first electrode disposed on the first conductive film through an opening formed in the second conductive film and the second insulating film, and having a first width;

a second electrode that is formed on the first electrode and having a second width; and

a wiring layer that is formed on the second electrode,

wherein a first width of the first electrode is wider than the second width of the second electrode.

2. The semiconductor memory device according to claim 1 , further comprising:

a first spacer film that is formed between the second electrode and the second conductive film.

3. The semiconductor memory device according to claim 2 , further comprising:

a second spacer film disposed between a side surface of the second electrode and a side surface of the first spacer film.

4. The semiconductor memory device according to claim 3 ,

wherein the second spacer film contacts an upper surface of the first electrode.

5. The semiconductor memory device according to claim 1 ,

wherein the first electrode comprises polysilicon.

6. The semiconductor memory device according to claim 1 ,

wherein the first spacer film comprises silicon nitride.

7. The semiconductor memory device according to claim 1 , wherein the opening extends into the second electrode.

8. A semiconductor memory device comprising:

a semiconductor substrate;

a first insulating film disposed on the semiconductor substrate;

a first conductive film disposed on the first insulating film;

a second insulating film disposed on the first conductive film;

a second conductive film disposed on the second insulating film;

an electrode contacting the first conductive film through an opening formed in the second conductive film and the second insulating film;

a first spacer film disposed between the second conductive film and the electrode; and

a wiring layer that is formed on the electrode,

wherein the wiring layer is disposed along an upper side surface of the first spacer film, and has a width, in an upper end of the first spacer film, wider than a width of an upper surface of the electrode.

9. The semiconductor memory device according to claim 8 ,

wherein the wiring layer has a first lower surface that comes into contact with the electrode and a second lower surface that does not come into contact with the electrode, and

wherein at least a portion of the second lower surface of the wiring layer is positioned lower than the first lower surface of the wiring layer.

10. The semiconductor memory device according to claim 8 ,

wherein the wiring layer contacts an inner side wall of the first spacer film.

11. The semiconductor memory device according to claim 8 , further comprising:

a second spacer film located between a side surface of the wiring layer and the upper side surface of the first spacer film.

12. The semiconductor memory device according to claim 11 ,

wherein the second spacer film contacts an upper surface of the electrode.

13. The semiconductor memory device according to claim 12 , further comprising:

a peripheral transistor having a gate electrode comprising a stack of conductive films; and

a third spacer film along a side surface of the gate electrode of the peripheral transistor,

wherein a material of the third spacer film is the same as a material of the second spacer film.

14. The semiconductor memory device according to claim 8 ,

wherein the electrode contains a polysilicon.

15. The semiconductor memory device according to claim 8 ,

wherein the first spacer film contains a silicon nitride film.

16. The semiconductor memory device according to claim 8 , further comprising:

a transistor that is provided with a gate electrode formed by stacking a plurality of conductive films,

wherein a position of the upper surface of the electrode is higher than a position of an upper surface of the gate electrode of the transistor.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 057016/0551 →
MERGER Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 057016/0586 →
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057016/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2015
From: MIYAZAKI, SHOICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034895/0086 →