IP Library Granted Patent US 9,717,157
Granted Patent B2
US 9,717,157 · App. 14/617,523 · Granted Jul 25, 2017

Computer modules with small thicknesses and associated methods of manufacturing

Inventors: Kevin Gibbons (Boise, ID); Tracy V. Reynolds (Boise, ID); David J. Corisis (Nampa, ID)
Assignee: Micron Technology, Inc.
H05K7/02H01L24/83H01L25/0657H01L25/105H05K1/111H05K1/182H05K1/183H05K3/3436H01L24/73H01L25/18H01L2224/16145H01L2224/73265H01L2225/0651H01L2225/06513H01L2225/06555H01L2225/107H01L2225/1023H01L2225/1058H01L2225/1088H01L2924/00014H01L2924/14H01L2924/19104H05K2201/10515H05K2201/10545H05K2201/10727H05K2203/1572Y10T29/4913Y10T29/49126
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Quick Facts
Patent No.
US 9,717,157
App. No.
14/617,523
Granted
Jul 25, 2017
Kind
B2
Abstract

Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

Claims (42)

1. A computer module, comprising:

a module substrate having a module material and an aperture extending at least partially into the module material, wherein the module substrate has an exterior surface; and

a microelectronic package carried by the module substrate, the microelectronic package having:

(a) a package substrate having a first side that faces the module substrate and a second side opposite the first side, wherein the second side is an outermost surface of the microelectronic package, and wherein the outermost surface of the microelectronic package is spaced outwardly apart from the exterior surface of the module substrate;

(b) a plurality of memory semiconductor dies carried in a stacked arrangement at only the first side of the package substrate such that all of the plurality of memory semiconductor dies are at least partially within an aperture, wherein individual memory semiconductor dies are aligned in a stacked direction, wherein the plurality of memory semiconductor dies include at least three memory semiconductor dies; and

(c) a processor die attached to the memory semiconductor dies in the aperture, wherein the processor die is attached to one of the plurality of memory semiconductor dies that is furthest away from the first side of the package substrate of the plurality of memory semiconductor dies;

wherein at least a portion of the plurality of semiconductor dies extends into the substrate material via the aperture.

2. The computer module of claim 1 wherein the module substrate includes a plurality of bond sites on the exterior surface of the module substrate and adjacent to the aperture, and wherein the microelectronic package includes a plurality of contact pads aligned with the individual bond sites.

3. The computer module of claim 1 wherein the module substrate includes a plurality of bond sites on the exterior surface of the module substrate and adjacent to the aperture, and wherein the microelectronic package includes a plurality of contact pads aligned with the individual bond sites, and further wherein the computer module includes a plurality of electric couplers between individual bond sites and corresponding contact pads while the semiconductor die extends into the substrate material via the aperture.

4. The computer module of claim 1 wherein the aperture has a depth equal to a thickness of the module substrate.

5. The computer module of claim 1 wherein the aperture has a depth less than a thickness of the module substrate.

6. The computer module of claim 1 wherein the aperture has a depth equal to a thickness of the module substrate, and wherein the plurality of memory semiconductor dies extends from the package substrate for a distance less than the depth of the aperture.

7. The computer module of claim 1 wherein the aperture has a depth equal to a thickness of the module substrate, and wherein the plurality of memory semiconductor dies extends from the package substrate for a distance less than half of the depth of the aperture.

8. The computer module of claim 1 wherein the aperture has a depth equal to a thickness of the module substrate, and wherein the plurality of memory semiconductor dies extends from the package substrate for a distance equal to or less than the depth of the aperture.

9. A microelectronic package system, comprising:

a substrate having a first surface, a second surface opposite the first surface, wherein the first and second surfaces define exterior surfaces of the substrate;

an aperture at least partially extends from the first surface to the second surface, wherein the aperture is configured to receive at least a portion of a microelectronic package;

a plurality of bond sites proximate to the aperture;

the microelectronic package at least partially received in the aperture, the microelectronic package including:

a package substrate with a first face that faces the substrate and a second face opposite the first face, wherein the second face is an outermost surface of the microelectronic package, and wherein the outermost surface of the microelectronic package is spaced outwardly apart from the first surface of the substrate;

a plurality of memory semiconductor dies carried in a stacked arrangement at only the first face of the package substrate, wherein individual memory semiconductor dies are aligned in a stacked direction, wherein the plurality of memory semiconductor dies includes at least three memory semiconductor dies; and

a processor die attached to one of the memory semiconductor dies in the aperture, wherein the processor die is attached to one of the plurality of memory semiconductor dies that is furthest away from the first face of the package substrate of the plurality of memory semiconductor dies.

10. The microelectronic package system of claim 9 wherein the aperture extends completely between the first and second surfaces.

11. The microelectronic package system of claim 9 wherein the aperture extends completely between the first and second surfaces, the aperture having a rectangular uniform cross-section between the first and second surfaces.

12. The microelectronic package system of claim 9 , further comprising a second package substrate with a first face that faces the substrate and a second face opposite the first face, wherein the first face of the second package substrate faces the first package substrate.

13. A computer module, comprising:

a substrate having an aperture extending at least partially into the substrate, wherein the substrate has an exterior surface; and

a microelectronic package carried by the substrate, the microelectronic package having:

(a) a package substrate having a first side that faces the substrate and a second side opposite the first side, wherein the second side is an outermost surface of the microelectronic package, and wherein the outermost surface of the package substrate is spaced outwardly apart from the exterior surface of the substrate;

(b) at least four memory semiconductor dies carried in a stacked arrangement at only the first side of the package substrate such that each of the memory dies is at least partially within the aperture, wherein individual memory semiconductor dies are aligned in a stacked direction; and

(c) a processor die attached to one of the memory dies in the aperture, wherein the processor die is attached to one of the at least four memory semiconductor dies that is furthest away from the first side of the package substrate of the plurality of memory semiconductor dies.

14. The computer module of claim 13 wherein the substrate includes a plurality of bond sites on the exterior surface of the substrate and adjacent to the aperture, and wherein the microelectronic package includes a plurality of contact pads aligned with the individual bond sites.

15. The computer module of claim 13 wherein the substrate includes a plurality of bond sites on the exterior surface of the substrate and adjacent to the aperture, and wherein the microelectronic package includes a plurality of contact pads aligned with the individual bond sites, and further wherein the computer module includes a plurality of electric couplers between individual bond sites and corresponding contact pads while the semiconductor die extends into the substrate via the aperture.

16. The computer module of claim 13 wherein the aperture has a depth equal to a thickness of the substrate.

17. The computer module of claim 13 wherein the aperture has a depth less than a thickness of the substrate.

18. A computer module, comprising:

a substrate having an aperture extending at least partially into the substrate, wherein the substrate has an exterior surface; and

two microelectronic packages carried by the substrate, the microelectronic packages each having:

(a) a package substrate having a first side that faces the substrate and a second side opposite the first side, wherein the second side is an outermost surface of the microelectronic package, and wherein the outermost surface of the package substrate is spaced outwardly apart from the exterior surface of the substrate;

(b) a plurality of memory semiconductor dies carried in a stacked arrangement at only the first side of the package substrate such that all of the memory dies are at least partially within the aperture, wherein individual memory semiconductor dies are aligned in a stacked direction, wherein the plurality of memory semiconductor dies includes at least three memory semiconductor dies; and

(c) a processor die attached to one of the memory dies in the aperture, wherein the processor die is attached to one of the plurality of memory semiconductor dies that is furthest away from the first side of the package substrate of the plurality of memory semiconductor dies.

19. The computer module of claim 18 wherein the plurality of memory dies are encapsulated in an encapsulant.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 14171584 · Feb 3, 2014
Division 12353773 · Jan 14, 2009
Related Publication 20150156908A1 · Jun 4, 2015