IP Library Granted Patent US 10,020,432
Granted Patent B2
US 10,020,432 · App. 14/617,668 · Granted Jul 10, 2018

Etched trenches in bond materials for die singulation, and associated systems and methods

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Quick Facts
Patent No.
US 10,020,432
App. No.
14/617,668
Granted
Jul 10, 2018
Kind
B2
Abstract

Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.

Claims (18)

1. A substrate, comprising:

a plurality of SST dies, wherein individual SST dies include a first semiconductor material, a second semiconductor material, an active material between the first and second semiconductor materials, and one or more contacts over the second semiconductor material;

a bond material adjacent the first semiconductor material and attached to the plurality of SST dies;

a silicon carrier substrate attached to the bond material, wherein one or more trenches extend through the first semiconductor material, active material, second semiconductor material, and bond material between neighboring SST dies, and wherein individual trenches have diverging lateral side portions and a bottom curved portion at least partially formed by the silicon carrier substrate; and

a protective material at least partially encapsulating the SST dies, wherein the protective material is adhered to the lateral side portions of the trenches, and wherein the contacts are only partially encapsulated by the protective material.

2. The substrate of claim 1 wherein the contacts are N-contacts.

3. The substrate of claim 2 wherein the N-contacts are electrically connected to the second semiconductor material of the individual SST dies, the substrate further comprising P-contacts electrically connected to the first semiconductor material of the individual SST dies.

4. The substrate of claim 1 wherein the protective material at least partially covers the bottom curved portion of individual trenches.

5. The substrate of claim 1 wherein the curved portion at least partially formed by the silicon carrier substrate is completely covered by the protective material.

6. The substrate of claim 1 wherein the lateral side portions are at least partially formed by the bond material and share a continuous curved surface with the curved portion at least partially formed by the silicon carrier substrate.

7. The substrate of claim 1 wherein the bond material comprises a metal or a metal alloy.

8. The substrate of claim 7 wherein the bond material comprises a first layer including tin (Sn), a second layer including tin, and a third layer, between the first and second layers, including nickel (Ni).

9. The substrate of claim 1 wherein the bottom curved portion of the individual trenches are part of an undercut portion beneath the individual SST dies.

10. An SST device, comprising:

an SST die having a first side including a plurality of contacts, a second side opposite the first side, and lateral side portions between the first and second sides;

a bond material attached to the SST die at the second side;

a silicon carrier substrate attached to the bond material, wherein an indentation extends through the SST die and bond material and at least partially through the silicon carrier substrate, wherein the indentation through the bond material and the silicon carrier substrate forms adjacent portions of a continuous curved surface, and wherein a width of the indentation increases in a direction away from the contacts; and

a protective material at least partially covering side portions of the SST die, a portion of each of the contacts, and a portion of the indentation of the silicon carrier substrate.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2018
From: ODNOBLYUDOV, VLADIMIR; SCHELLHAMMER, SCOTT D.; FREI, JEREMY S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045614/0744 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2017
From: ODNOBLYUDOV, VLADIMIR; SCHELLHAMMER, SCOTT D.; FREI, JEREMY S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041660/0473 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →