Memory device having address and command selectable capabilities

1. A method, comprising:

receiving a first write command for programming information to a first portion of a memory; and

selecting, based on a reliability of the information to be stored in the first portion of the memory, a first write circuit from a plurality of write circuits for executing the first write command.

2. The method of claim 1 , wherein the information to be stored in the first portion of the memory comprises an operating system code or a program code.

3. The method of claim 1 , further comprising:

receiving a second write command for programming information to a second portion of the memory; and

selecting, based on a reliability of the information to be stored in the second portion of the memory, a second write circuit from the plurality of write circuits for executing the second write command,

wherein the reliability of the information to be stored in the first portion of the memory is greater than the reliability of the information to be stored in the second portion of the memory.

4. The method of claim 3 , further comprising executing the first write command using the first write circuit and executing the second write command using the second write circuit, wherein the first write circuit is configured to execute the first write command with an accuracy higher than an accuracy with which the second write circuit is configured to execute the second write command.

5. The method of claim 3 , further comprising executing the first write command using the first write circuit, wherein executing the first write command comprises performing a verify process.

6. The method of claim 3 , further comprising executing the first write command using the first write circuit, wherein executing the first write command comprises applying a plurality of programming pulses.

7. The method of claim 3 , further comprising executing the second write command using the second write circuit, wherein executing the second write command comprises applying a single programming pulse.

8. The method of claim 3 , further comprising executing the first write command using the first write circuit and executing the second write command using the second write circuit, wherein the second write command is executed with a speed higher than a speed with which the first write command is executed.

9. The method of claim 3 , further comprising partitioning the memory into a first partition and a second partition by associating the first portion of the memory with the first partition and associating the second portion of the memory with the second partition,

wherein the first partition is configured to store information having a reliability higher than a reliability of information stored in the second partition.

10. A memory device, comprising:

a memory array; and

a memory controller configured to:

receive a first write command for programming information to a first memory portion of the memory array;

select, based on a reliability of the information to be stored in the first memory portion, a first write circuit from a plurality of write circuits for executing the first write command.

11. The device of claim 10 , further comprising a second memory portion, and wherein the memory controller is further configured to:

receive a second write command for programming information to the second memory portion;

select, based on a reliability of the information to be stored in the second memory portion, a second write circuit of the plurality of write circuits for executing the second write command,

wherein the reliability of the information to be stored in the first memory portion is greater than the reliability of the information to be stored in the second memory portion.

12. The device of claim 11 , wherein the memory array further comprises the second memory portion.

13. The device of claim 12 , wherein the memory controller is further configured to partition the memory array into a first memory partition and a second memory partition by associating the first memory portion with the first memory partition and associating the second memory portion with the second memory partition,

wherein the first memory partition is configured to store information having a reliability higher than a reliability of information stored in the second memory partition.

14. The device of claim 11 , wherein the first write circuit is configured to execute the first write command by applying multiple programming pulses, and the second write circuit is configured to execute the second write command by applying a single programming pulse.

15. The device of claim 11 , wherein the information to be stored in the first memory portion comprises an operating system code or a program code.

16. The device of claim 11 , wherein the first write circuit is configured to execute the first write command and the second write circuit is configured to execute the second write command, and wherein an accuracy with which the first write circuit is configured to execute the first write command is higher than an accuracy with which the second write circuit is configured to execute the second write command.

17. The device of claim 11 , wherein the first write circuit is configured to execute the first write command and the second write circuit is configured to execute the second write command, and wherein a speed with which the second write circuit is configured to execute the second write command is greater than a speed with which the first write circuit is configured to execute the first write command.

18. A system, comprising:

a memory array;

a memory controller configured to:

receive a first write command for programming information to a first portion of the memory array;

select, based on a reliability of the information to be stored in the first portion of the memory array, a first write circuit from a plurality of write circuits for executing the first write command; and

a processor configured to initiate a command for accessing the memory array.

19. The system of claim 18 , further comprising a second memory portion, and wherein the memory controller is further configured to:

receive a second write command for programming information to the second memory portion;

select, based on a reliability of the information to be stored in the second memory portion, a second write circuit from the plurality of write circuits for executing the second write command,

wherein the reliability of the information to be stored in the first portion of the memory array is greater than the reliability of the information to be stored in the second memory portion.

20. The system of claim 19 , wherein the first write circuit is configured to execute the first write command and the second write circuit is configured to execute the second write command, and wherein an accuracy with which the first write circuit is configured to execute the first write command is higher than an accuracy with which the second write circuit is configured to execute the second write command.