IP Library Granted Patent US 9,853,156
Granted Patent B2
US 9,853,156 · App. 14/618,414 · Granted Dec 26, 2017

Source/drain contacts for non-planar transistors

Inventors: Sameer S. Pradhan (Portland, OR); Subhash M. Joshi (Hillsboro, OR); Jin-Sung Chun (Hillsboro, OR)
Assignee: Intel Corporation
H01L29/785H01L21/02H01L21/02532H01L21/283H01L21/32053H01L23/48H01L29/16H01L29/41791H01L29/456H01L29/6656H01L29/66545H01L29/66666H01L29/66795H01L29/78H01L29/7851H01L2924/0002
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Quick Facts
Patent No.
US 9,853,156
App. No.
14/618,414
Granted
Dec 26, 2017
Kind
B2
Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Claims (33)

1. A microelectronic device, comprising:

a silicon-containing non-planar transistor fin;

a source/drain region in the silicon-containing non-planar fin;

a source/drain contact adjacent the source/drain region, wherein the source/drain contact comprises a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the source/drain region;

a titanium silicide interface disposed between the source/drain region and the titanium-containing contact interface layer; and

a non-planar transistor gate over the non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, and wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer and/or abuts at least a portion of the capping structure.

2. The microelectronic device of claim 1 , wherein the conductive contact material comprises tungsten.

3. The microelectronic device of claim 1 , wherein the titanium silicide interface resides substantially only between the source/drain region and the titanium-containing contact interface layer.

4. A method of fabricating a microelectronic device, comprising:

forming a silicon-containing non-planar transistor fin;

forming a source/drain region in the silicon-containing non-planar fin;

forming a dielectric material over the source/drain region;

forming a contact opening through the dielectric material to expose a portion of the source/drain region;

conformally depositing a titanium-containing contact interface layer within the contact opening to abut the source/drain region;

depositing a conductive contact material within the contact opening to abut the titanium-containing contact interface layer; and

forming a titanium silicide interface between the source/drain region and the titanium-containing contact interface layer.

5. The method of claim 4 , wherein conformally depositing the titanium-containing contact interface layer comprises depositing a substantially pure titanium contact interface layer.

6. The method of claim 4 , wherein depositing a conductive contact material within the contact opening comprises depositing tungsten within the contact opening.

7. The method of claim 4 , wherein forming the titanium silicide interface between the source/drain region and the titanium-containing contact interface layer comprises forming the titanium silicide interface between the source/drain region and the titanium-containing contact interface layer by heating the source/drain region and the titanium-containing contact interface layer.

8. The method of claim 4 , wherein forming the titanium silicide interface comprises forming the titanium silicide substantially only between the source/drain region and the titanium-containing contact interface layer.

9. The method of claim 4 , wherein forming the non-planar transistor gate comprises forming gate spacers, forming a gate electrode recessed between the gate spacers and disposing a capping structure on the recessed gate electrode between the gate spacers.

10. The method of claim 9 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of one non-planar transistor gate spacer.

11. The method of claim 10 , wherein forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of one non-planar transistor gate spacer.

12. The method of claim 9 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of the capping structure.

13. The method of claim 12 , wherein the forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of the capping structure.

14. A microelectronic device, comprising:

a silicon-containing non-planar transistor fin;

a source/drain region in the silicon-containing non-planar fin;

a source/drain contact adjacent the source/drain region, wherein the source/drain contact comprises a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the source/drain region, wherein the titanium-containing contact interface layer comprises substantially pure titanium;

a titanium silicide interface disposed between the source/drain region and the titanium- containing contact interface layer; and

a non-planar transistor gate over the non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, and wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer and/or abuts at least a portion of the capping structure.

15. The microelectronic device of claim 14 , wherein the conductive contact material comprises tungsten.

16. The microelectronic device of claim 14 , wherein the titanium silicide interface resides substantially only between the source/drain region and the titanium-containing contact interface layer.

Continuity (2)
Continuation 13992550
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