IP Library Granted Patent US 9,831,873
Granted Patent B2
US 9,831,873 · App. 14/618,953 · Granted Nov 28, 2017

Method and apparatus for simultaneous processing of multiple functions

Inventors: Adrian Stoica (Altadena, CA); Radu Andrei (Shelby Township, MI)
Assignee: California Institute of Technology
H03K19/0002G06F7/00G06F7/49H03K19/08
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Quick Facts
Patent No.
US 9,831,873
App. No.
14/618,953
Granted
Nov 28, 2017
Kind
B2
Abstract

Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Claims (20)

1. A logic gate comprising:

a decoder;

a plurality of Boolean gates; and

an encoder;

where the logic gate:

determines a logic level selected from at least three input logic levels based on a first voltage scale of a received input signal using the decoder;

determines a Boolean output by transmitting the logic level through the plurality of Boolean gates; and

determines an output logic level selected from at least three output logic levels based on a second voltage scale using the Boolean output transmitted to the encoder.

2. The logic gate of claim 1 , wherein the decoder decodes the logic level into a set of binary values.

3. The logic gate of claim 1 , wherein the first voltage scale is the same as the second voltage scale.

4. The logic gate of claim 1 , wherein the first voltage scale is not the same as the second voltage scale.

5. The logic gate of claim 1 , wherein the first voltage scale is a sequence of monotonically increasing voltage levels.

6. The logic gate of claim 1 , wherein the first voltage scale is a sequence of equally spaced voltage levels.

7. The logic gate of claim 1 , wherein the second voltage scale is a sequence of monotonically increasing voltage levels.

8. The logic gate of claim 1 , wherein the second voltage scale is a sequence of equally spaced voltage levels.

9. The logic gate of claim 1 , wherein the at least three input logic levels have four states.

10. The logic gate of claim 1 , wherein the Boolean gates simultaneously determine the Boolean output.

11. The logic gate of claim 1 , wherein the logic levels are transmitted to the plurality of Boolean gates on a plurality of separate channels.

12. The logic gate of claim 11 , wherein each channel in the plurality of separate channel transmits a portion of the Boolean output to the encoder.

13. The logic gate of claim 1 , wherein the Boolean gates are selected from the group consisting of AND, OR, XOR, NAND, NOR, and NAND3.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2016
From: STOICA, ADRIAN
To: CALIFORNIA INSTITUTE OF TECHNOLOGY
Reel/Frame 040218/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2016
From: ANDREI, RADU
To: CALIFORNIA INSTITUTE OF TECHNOLOGY
Reel/Frame 040218/0406 →
CONFIRMATORY LICENSE Recorded Apr 9, 2015
From: CALIFORNIA INSTITUTE OF TECHNOLOGY
To: NASA
Reel/Frame 035653/0895 →
Continuity (6)
Division 13235188 · Sep 16, 2011
Continuation In Part 12393562 · Feb 26, 2009
Provisional Application 61383488 · Sep 16, 2010
Provisional Application 61067666 · Feb 29, 2008
Related Publication 20160233862A1 · Aug 11, 2016
Related Publication 20170244410A9 · Aug 24, 2017