Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.
1. An apparatus comprising;
a string of charge storage devices formed along a vertical channel of semiconductor material and coupled together in series, wherein tire string of charge storage devices includes multiple memory cells formed vertically along the vertical channel;
a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel and included in a layer of gate polysilicon;
a dielectric isolation barrier formed in the layer of gate polysilicon;
a first isolation layer comprising a long surface and a short surface above the layer of gate polysilicon and the dielectric barrier;
a drain region of the SGD transistor within the first isolation layer; and
a second isolation layer comprising a long surface and a short surface above the first isolation layer and the drain region, and the long surface of the second isolation layer contacting the long surface of the first isolation layer, wherein a conductive contact extends through the second isolation layer in electrical contact with the drain region of the SGD transistor, and wherein the multiple memory cells extend vertically from the SGD transistor.
2. The apparatus of claim 1 , wherein the gate region of the SGD transistor includes a layer of polysilicon at least partially surrounding the vertical channel, and wherein the dielectric barrier is formed within the layer of polysilicon.
3. The apparatus of claim 1 , wherein the gate region of the SGD transistor includes a layer of polysilicon at least partially surrounding the vertical channel, and wherein the first isolation layer extends from a top surface of the layer of polysilicon to the top surface of the vertical channel.
4. The apparatus of claim 1 , wherein the gate region of the SGD transistor includes a layer of polysilicon at least partially surrounding the vertical channel, and wherein the first isolation layer extends from the layer of polysilicon to the top surface of the drain region.
5. The apparatus of claim 1 , wherein the vertical channel is a channel region for the charge storage devices and the SGD transistor.
6. The apparatus of claim 1 , wherein the second isolation layer includes an oxide sub-layer and a nitride sub-layer.
7. The apparatus of claim 1 , wherein the vertical string of charge storage devices are formed as a stack, including layers of charge storage devices alternating with layers of dielectric material, and wherein the vertical channel includes a pillar of semiconductor material formed in the stack.
8. The apparatus of claim 7 , wherein one or more of layers of dielectric material include alumina.
9. The apparatus of claim 7 , wherein one or more of the layers of charge storage devices include a transistor having a control gate and a floating gate.
10. The apparatus of claim 1 , wherein the vertical channel includes p-type polysilicon and the drain region includes n-type polysilicon.
11. The apparatus of claim 1 , wherein the vertical channel includes n-type polysilicon and the drain region includes p-type polysilicon.
12. The apparatus of claim 1 , wherein the vertical string of charge storage devices are included in a NAND memory device.
13. A memory device comprising: a string of charge storage devices formed along a vertical channel of semiconductor material
and coupled together in series, wherein the string of charge storage devices includes a plurality of memory cells formed vertically along the vertical channel;
a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel and included in a layer of gate polysilicon;
a dielectric barrier formed in the layer of gate polysilicon;
a first isolation layer comprising a long surface and a short surface above the layer of gate polysilicon and the dielectric barrier;
a drain region of the SGD transistor at an end of the vertical channel and within the first isolation layer;
a second isolation layer comprising a long surface and a short surface above the first isolation layer and the drain region, and the long surface of the second isolation layer contacting the long surface of the first isolation layer, wherein a conductive contact extends through the second isolation in electrical contact with the drain region of the SGD transistor at the end of the vertical channel and the plurality of memory cells extend vertically from the SGD transistor; and
a data line in electrical contact with the conductive contact.
14. The memory device of claim 13 , wherein the gate region of the SGD transistor includes a layer of polysilicon at least partially surrounding the vertical channel, and wherein the dielectric barrier is formed within the layer of polysilicon.