Direct memory access controller and system for accessing channel buffer
A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.
1. A direct memory access (DMA) controller comprising:
a channel group comprising a plurality of DMA channels;
a buffer group comprising a plurality of buffers configured to store data;
a processor interface directly connecting a processor core to the buffer group and configured to:
receive information representing a first operation and including information for designating one of the plurality of DMA channels included in the channel group from the processor core;
corresponding to the first operation, transmit data which is stored in a buffer among the plurality of buffers included in the buffer group to the processor core; and
corresponding to the first operation, store data which is processed by the processor core in the buffer among the plurality of buffers included in the buffer group;
a slave interface configured to receive information representing a second operation sent by the processor core to the channel group, and allocate the second operation to at least one DMA channel from among the plurality of DMA channels included in the channel group; and
a master interface group connected to the buffer group, and comprising at least one master interface configured to transmit and receive data corresponding to the second operation to and from an external memory,
wherein the buffer is connected to the designated DMA channel,
wherein the at least one DMA channel is configured to operate in a mode from among a first mode in which data included in a first slave device is stored in the buffer and a second mode in which data stored in the buffer is transmitted to a second slave device,
wherein the first slave device and the second slave device are connected to the master interface group,
wherein at least two buffers from among the plurality of buffers are connected to each other and are configured to input and output the data as a double buffer,
wherein at least one buffer from among the at least two buffers connected to each other is configured to input and output the data in a first-in-first-out (FIFO) manner, and
wherein remaining buffers from among the at least two buffers connected to each other are configured to input and output the data in a random access manner.
2. The DMA controller of claim 1 , wherein the processor interface and the slave interface are physically included in a same interface.
3. The DMA controller of claim 1 , further comprising an internal bus connected to the buffer group, the master interface group, and the processor interface.
4. The DMA controller of claim 1 , wherein the plurality of buffers included in the buffer group are configured to input and output data in a first-in-first-out (FIFO) manner.
5. The DMA controller of claim 1 , wherein the plurality of buffers included in the buffer group are configured to input and output data in a random access manner based on addresses of entries.
6. The DMA controller of claim 5 , wherein the random access manner comprises one of a first type in which the data is input and output to and from an entry included in the buffer based on an address of the entry generated according to a preset pattern, a second type in which the data is input and output to and from the entry based on an address of the entry generated according to an input stride, and a third type in which the data is input and output to and from the entry based on an address of the entry generated according to an order pattern defined in a pattern register.
7. A system comprising:
a direct memory access (DMA) controller; and
a processor core connected to the DMA controller,
wherein the DMA controller comprises:
a channel group comprising a plurality of DMA channels;
a buffer group comprising a plurality of buffers configured to store data;
a processor interface directly connecting the processor core to the buffer group and configured to:
receive information representing a first operation and including information for designating one of the plurality of DMA channels included in the channel group from the processor core;
corresponding to the first operation, transmit data which is stored in a buffer among the plurality of buffers included in the buffer group to the processor core; and
corresponding to the first operation, store data which is processed by the processor core in the buffer among the plurality of buffers included in the buffer group; and
a slave interface configured to receive information representing a second operation sent by the processor core to the channel group, and allocate the second operation to at least one DMA channel from among the plurality of DMA channels included in the channel group; and
a master interface group connected to the buffer group, and comprising at least one master interface configured to transmit and receive data corresponding to the second operation to and from an external memory,
wherein the buffer is connected to the designated DMA channel,
wherein the at least one DMA channel is configured to operate in a mode from among a first mode in which data included in a first slave device is stored in the buffer and a second mode in which data stored in the buffer is transmitted to a second slave device,
wherein the first slave device and the second slave device are connected to the master interface group,
wherein at least two buffers from among the plurality of buffers are connected to each other and are configured to input and output the data as a double buffer,
wherein at least one buffer from among the at least two buffers connected to each other is configured to input and output the data in a first-in-first-out (FIFO) manner, and
wherein remaining buffers from among the at least two buffers connected to each other are configured to input and output the data in a random access manner.
8. The system of claim 7 , wherein the processor interface and the slave interface are physically included in a same interface.
9. The system of claim 7 , wherein the plurality of buffers included in the buffer group are configured to input and output data in a first-in-first-out (FIFO) manner or in a random access manner based on addresses of entries.
10. The system of claim 9 , wherein the random access manner comprises one of a first type in which the data is input and output to and from an entry included in the buffer based on an address of the entry generated according to a preset pattern, a second type in which the data is input and output to and from the entry based on an address of the entry generated according to an input stride, and a third type in which the data is input and output to and from the entry based on an address of the entry generated according to an order pattern defined in a pattern register.
11. The system of claim 7 , wherein, based on a signal transmitted from a DMA channel, each of the at least two buffers are configured to input and output the data in a first-in-first-out (FIFO) manner, or the at least two buffers are connected to each other as a multi-buffer.