IP Library › Granted Patent US 9,368,486
Granted Patent B2
US 9,368,486 · App. 14/621,766 · Granted Jun 14, 2016

Direct connected silicon controlled rectifier (SCR) having internal trigger

Inventors: Zhixin Wang (Austin, TX); Juin Jei Liou (Oviedo, FL); Ruei-Cheng Sun (Tainan, TW)
Assignee: Allegro Microsystems, LLC
H01L27/0262
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Quick Facts
Patent No.
US 9,368,486
App. No.
14/621,766
Granted
Jun 14, 2016
Kind
B2
Abstract

In one aspect, a direct connected silicon control rectifier (DCSCR) includes a substrate having a semiconductor surface, a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor formed in the semiconductor surface. The parasitic PNP bipolar transistor includes a p+ emitter, an nbase and a pcollector and the parasitic NPN bipolar includes an n+ emitter, a pbase and an ncollector. The DCSCR also includes an electrically conductive line connecting an n+ contact to the nbase to a p+ contact to the pbase so that the nbase and the pbase are shorted.

Claims (30)

1. A direct connected silicon control rectifier (DCSCR), comprising:

a substrate having a semiconductor surface;

at least one n-well;

a parasitic PNP bipolar transistor and parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-base and a p-collector;

a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, a p-base and an n-collector; and

an electrically conductive line connecting an n+ contact of the n-base to a p+ contact of the p-base so that the n-base and the p-base are shorted,

wherein the semiconductor surface is p-type and provides the p-base, and

wherein the n-well provides the n-base.

2. The DCSCR of claim 1 , further comprising functional circuitry formed in and on the semiconductor surface; wherein the DCSCR is hooked in parallel with at least a first sub-circuit of the functional circuitry between a input/output (I/O) bond pad and a ground pad of the functional circuitry.

3. The DCSCR of claim 1 , wherein the DCSCR is coupled to an ESD detector circuit.

4. The DCSCR of claim 1 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

5. A twin-well direct connected silicon control rectifier (DCSCR), comprising:

a substrate having a semiconductor surface;

a parasitic PNP bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-well providing an n-base and a p-well providing a p-collector;

a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, the p-well providing a p-base and the n-well providing an n-collector; and

an electrically conductive line connecting an n+ contact of the n-well to a p+ contact of the p-well so that the n-base and the p-base are shorted.

6. The DCSCR of claim 5 , wherein the DCSCR is coupled to an ESD detector circuit.

7. The DCSCR of claim 5 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

8. The DCSCR of claim 5 , further comprising functional circuitry formed in and on the semiconductor surface; wherein the DCSCR is hooked in parallel with at least a first sub-circuit of the functional circuitry between a input/output (I/O) bond pad and a ground pad of the functional circuitry.

9. A direct connected silicon control rectifier (DCSCR), comprising:

a substrate having a semiconductor surface;

an n-well;

a p-well;

a parasitic PNP bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-base and a p-collector;

a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, a p-base and an n-collector; and

an electrically conductive line connecting an n+ contact of the n-base to a p+ contact of the p-base so that the n-base and the p-base are shorted,

wherein the n-well provides the n-base and the p-well provides the p-base, and

wherein the n+ emitter is not in direct contact with the electrically conductive line.

10. The DCSCR of claim 9 , wherein the DCSCR is coupled to an ESD detector circuit.

11. The DCSCR of claim 9 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: WANG, ZHIXIN; LIOU, JUIN JEI; SUN, RUEI-CHENG
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 035067/0233 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2015
From: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
To: LIOU, JUIN JEI; WANG, ZHIXIN; SUN, RUEI-CHENG
Reel/Frame 035040/0964 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2015
From: WANG, ZHIXIN; LIOU, JUIN JEI; SUN, RUEI-CHENG
To: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
Reel/Frame 035022/0467 →
Continuity (2)
Provisional Application 61940586 · Feb 17, 2014
Related Publication 20150236011A1 · Aug 20, 2015