Resurf high voltage diode
View Patent ↗A trench-isolated RESURF diode structure ( 100 ) is provided which includes a substrate ( 150 ) in which is formed anode ( 130, 132 ) and cathode ( 131 ) contact regions separated from one another by a shallow trench isolation region ( 114, 115 ), along with a buried cathode extension region ( 104 ) formed under a RESURF anode extension region ( 106, 107 ) such that the cathode extension region ( 104 ) extends beyond the cathode contact ( 131 ) to be sandwiched between upper and lower regions ( 103, 106, 107 ) of opposite conductivity type.
1. A semiconductor diode device, comprising:
a semiconductor substrate region;
an isolation structure for electrically isolating the semiconductor substrate region comprising a buried insulation layer formed under the semiconductor substrate region, a deep trench isolation region formed around the semiconductor substrate region with one or more insulating dielectric layers, and at least a first shallow trench isolation region located on a surface of the semiconductor substrate region, where the buried insulation layer and the deep trench isolation region are connected;
a heavily doped first terminal contact region of a first conductivity type formed in the semiconductor substrate region;
a heavily doped second terminal contact region of a second conductivity type formed in the semiconductor substrate region to be spaced apart from the heavily doped first terminal contact region;
a first terminal extension region of the first conductivity type located in the semiconductor substrate region to contain the heavily doped first terminal contact region and to extend part way to the heavily doped second terminal contact region;
a second terminal extension region of the second conductivity type located in the semiconductor substrate region to contain the heavily doped second terminal contact region and to extend below the first terminal extension region and where the second terminal extension region comprises a buried region with the second conductivity type which extends beyond the heavily doped first terminal contact region to contact the deep trench isolation region.
2. The semiconductor diode device of claim 1 , where the heavily doped first terminal contact region and first terminal extension region formed with material of the first conductivity type comprise either an anode terminal or a cathode terminal, and where the heavily doped second terminal contact region and the second terminal extension region formed with material of the second conductivity type comprise, respectively, either a cathode terminal or an anode terminal.
3. The semiconductor diode device of claim 1 , where the first terminal extension region and second terminal extension region form a p-n junction at a bottom surface of the first shallow trench isolation region.
4. The semiconductor diode device of claim 1 , where the first terminal extension region comprises a region of the first conductivity type at the surface of the semiconductor substrate region between the heavily doped first terminal and second terminal contact regions.
5. The semiconductor diode device of claim 1 , where the semiconductor substrate region comprises a semiconductor-on-insulator substrate comprising the buried insulation layer.
6. The semiconductor diode device of claim 1 , where the first terminal extension region overlaps with the second terminal extension region to form a p-n junction such that the first terminal extension region and second terminal extension region are positioned to mutually deplete each other during operation.
7. The semiconductor diode device of claim 1 , further comprising a conductive electrode layer formed on the first shallow trench isolation region which is positioned over a lateral p-n junction formed at a bottom surface of the first shallow trench isolation region between the first terminal extension region and second terminal extension region.
8. An integrated circuit device, comprising:
a semiconductor substrate region;
an isolation structure for electrically isolating the semiconductor substrate region comprising a deep trench isolation region and a buried insulation layer formed around the semiconductor substrate region where the buried insulation layer and the deep trench isolation region are connected;
at least a first shallow trench isolation region located on a surface of the semiconductor substrate region;
a heavily doped first terminal contact region of a first conductivity type formed in the semiconductor substrate region;
a heavily doped second terminal contact region of a second conductivity type formed in the semiconductor substrate region to be spaced apart from the heavily doped first terminal contact region;
a first selectively implanted terminal extension region of the first conductivity type located in the semiconductor substrate region to contain the heavily doped first terminal contact region and to extend part way to the heavily doped second terminal contact region;
a second selectively implanted terminal extension region of the second conductivity type located in the semiconductor substrate region to contain the heavily doped second terminal contact region; and
a buried RESURF extension region of the second conductivity type which extends from the second selectively implanted terminal extension region and below and laterally past the heavily doped first terminal contact region,
wherein the first selectively implanted terminal extension region and second selectively implanted terminal extension region form a lateral p-n junction at a bottom surface of the first shallow trench isolation region laterally spaced apart from the heavily doped first terminal contact region and heavily doped second terminal contact region and where the second selectively implanted terminal extension region comprises a buried region of the second conductivity type which extends beyond the heavily doped first terminal contact region to contact the deep trench isolation region.
9. The integrated circuit device of claim 8 , where the heavily doped first terminal contact region and first selectively implanted terminal extension region form either an anode terminal or a cathode terminal of a diode, and where the heavily doped second terminal contact region and the second selectively implanted terminal extension region form, respectively, either a cathode terminal or an anode terminal of the diode.
10. The integrated circuit device of claim 8 , where the second selectively implanted terminal extension region comprises an upper region around the heavily doped second terminal contact region which extends down to the buried RESURF extension region.
11. The integrated circuit device of claim 8 , where the integrated circuit device comprises a high voltage diode device.
12. The integrated circuit device of claim 8 , further comprising a conductive electrode layer formed on the first shallow trench isolation region to overlap the lateral p-n junction between the first selectively implanted terminal extension region and second selectively implanted terminal extension region.
13. A high voltage RESURF diode device, comprising:
a semiconductor substrate;
an isolation structure for electrically isolating the semiconductor substrate comprising a deep trench isolation region and a buried insulation layer formed around the semiconductor substrate where the buried insulation layer and the deep trench isolation region are connected;
a cathode region form in the semiconductor substrate;
an anode region form in the semiconductor substrate; and
at least a first shallow trench isolation region located on a surface of the semiconductor substrate to separate a cathode contact from an anode contact,
where the cathode region comprises an upper region formed around the cathode contact and extending down to a buried RESURF extension region which extends laterally below the anode region and past the anode contact to contact the deep trench isolation region such that the upper region and the anode region form a lateral p-n junction at a bottom surface of the first shallow trench isolation region between the anode contact and cathode contact.
14. The high voltage RESURF diode device of claim 13 , where the anode region comprises an anode extension region formed at a surface of the semiconductor substrate to extend part way to the cathode contact and to overlap with the buried RESURF region to form a p-n junction such that the anode extension region and buried RESURF region are positioned to mutually deplete each other during operation.
15. The high voltage RESURF diode device of claim 13 , further comprising a conductive electrode layer formed on the first shallow trench isolation region to overlap the lateral p-n junction between the upper region and the anode region.