IP Library Granted Patent US 9,497,141
Granted Patent B2
US 9,497,141 · App. 14/624,207 · Granted Nov 15, 2016

Switch point having look-ahead bypass

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Quick Facts
Patent No.
US 9,497,141
App. No.
14/624,207
Granted
Nov 15, 2016
Kind
B2
Abstract

A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. Look-ahead information and corresponding packet are received at an input port. A first stage look-ahead request is generated from the look-ahead information. A second stage look-ahead request is generated in response to the first stage look-ahead request being not granted. And in response to the second stage look-ahead request being granted, transmitting a packet through the switch point using the look-ahead pipeline.

Claims (50)

1. In a network having a plurality of switch points, each switch point having a plurality of ports for transmitting packets from a source device to a destination device, and each switch point having both a main multi-stage pipeline between ports of the plurality of ports and a look-ahead pipeline between the ports of the plurality of ports, wherein the look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline, a method comprising:

receiving a packet and look-ahead information corresponding to the packet at a port of a switch point;

generating a first stage look-ahead request from the look-ahead information;

determining that the first stage look-ahead request is not granted;

generating a second stage look-ahead request from the first stage look-ahead request in response to the first stage look-ahead request not being granted;

determining that the second stage look-ahead request is granted;

in response to the second stage look-ahead request being granted, transmitting the packet through the switch point using the look-ahead pipeline; and in response to the second stage look-ahead request not being granted:

generating a third stage look-ahead request from the second stage look-ahead request;

determining that the third stage look-ahead request is not granted; and

transmitting the packet through the switch point using the main multi-stage pipeline.

2. The method of claim 1 , wherein transmitting the packet through the main multi-stage pipeline comprises:

storing the packet in a storage element of a virtual channel of the switch point;

arbitrating for access to the virtual channel;

allocating a switch traversal path through the switch point; and

transmitting the packet through the allocated switch traversal path.

3. The method of claim 1 , wherein transmitting the packet through the main multi-stage pipeline further comprises transmitting the packet through the main multi-stage pipeline in four clock cycles, and transmitting the packet through the look-ahead pipeline comprises transmitting the packet through the look-ahead pipeline in less than four clock cycles.

4. The method of claim 1 , wherein the plurality of switch points are connected together in a mesh configuration.

5. The method of claim 1 , wherein the packet begins transiting the main multi-stage pipeline concurrently with generating the first stage look-ahead request.

6. The method of claim 1 , wherein in response to one of the first stage look-ahead request and second stage look-ahead request being granted, the transiting of the main multi-stage pipeline is cancelled.

7. A method comprising: receiving a packet and look-ahead information corresponding to the packet at a port of a switch point, the switch point being one of a plurality of switch points configured as network; the packet being routed through the switch point between a source and a destination;

generating a first stage look-ahead request from the look-ahead information;

determining that the first stage look-ahead request is not granted;

generating a second stage look-ahead request from the first stage look-ahead request in response to the first stage look-ahead request not being granted;

determining that the second stage look-ahead request is granted; and

transmitting the packet through the switch point using a look-ahead pipeline in response to the second stage look-ahead request being granted, the look-ahead pipeline having fewer pipelining stages than a main multi-stage pipeline of the switch point;

generating a third stage look-ahead request from the second stage look-ahead request;

in response to determining that the third stage look-ahead request is granted, transmitting the packet through the switch point using the look-ahead pipeline; and

in response to determining that the third stage look-ahead request is not granted, transmitting the packet through the switch point using the main multi-stage pipeline.

8. The method of claim 7 , wherein transmitting the packet through the main multi-stage pipeline comprises:

storing the packet in a storage element of the switch point;

arbitrating a portion of a path between the source and the destination;

allocating a switch traversal path through the switch point; and

transmitting the packet through the allocated switch traversal path.

9. The method of claim 7 , wherein the plurality of switch points are connected together to form a network in a mesh configuration.

10. The method of claim 7 , wherein the packet begins transiting the main multi-stage pipeline concurrently with generating the first stage look-ahead request.

11. The method of claim 7 , wherein in response to the first stage look-ahead request being granted, the transiting of the main multi-stage pipeline is cancelled.

12. The method of claim 7 , wherein the switch point is implemented on a single integrated circuit die.

13. A switch point having a plurality of ports, the switch point comprising:

a main multi-stage pipeline coupled to the plurality of ports, the multi-stage pipeline having a plurality of pipelining stages for transmitting a packet of information between a selected input port and a selected output port of the plurality of ports; and

a look-ahead pipeline coupled to the plurality of ports, the look-ahead pipeline having fewer pipelining stages than the main multi-stage pipeline, the look-ahead pipeline for transmitting the packet of information between the input port and the selected output port,

wherein the look-ahead pipeline having a first look-ahead stage, a second look-ahead stage, and a third look-ahead stage, the first look-ahead stage for providing a first look-ahead request, the packet of information being transmitted through the look-ahead pipeline in response to the first look-ahead request being granted, the second look-ahead stage for providing a second look-ahead request, the second look-ahead request for requesting use of the look-ahead pipeline for the packet of information in response to the first look-ahead request not being granted, and the third look-ahead stage for providing a third look-ahead request, the third look-ahead request being provided in response to the first and second look-ahead requests not being granted, wherein the packet of information being transmitted through the look-ahead pipeline in response to the third look-ahead request being granted, and wherein the packet of information being transmitted through the main multi-stage pipeline in response to the third look-ahead request not being granted.

14. The switch point of claim 13 , wherein the main multi-stage pipeline further comprises:

a plurality of storage elements;

arbitrator coupled to the plurality of storage elements;

a plurality of switches for interconnecting the plurality of ports, access to the plurality of switches by the packet being arbitrated for using the arbitrator; and

allocation logic coupled to the plurality of switches, the allocation logic for allocating use of the plurality of switches for the packet.

15. The switch point of claim 13 , wherein the look-ahead pipeline further comprises the first and second look-ahead stages being coupled in series to the plurality of switches.

16. The switch point of claim 14 , wherein the allocation logic further comprises:

fast allocation and arbitrator logic for allocating use of the plurality of switches when the packet is being transmitted using the look-ahead pipeline; and

slow allocation and arbitrator logic for allocating use of the plurality of switches when the packet is being transmitted using the main multi-stage pipeline.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0341 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0359 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0974 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0112 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0095 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2015
From: NGUYEN, THANG Q.; BANSE, MARK A.; DESHPANDE, SANJAY R.; LARSON, JOHN E.; MORALES, FERNANDO A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034974/0307 →