Electronic device for communicating between a microcontroller unit (MCU) and a host processor and related methods
An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.
1. An electronic device for communicating between a microcontroller unit (MCU) and a host processor, the electronic device comprising:
a system clock configured to be switchable between an active state and an inactive state;
an SPI clock configured to be switchable between an active state and an inactive state;
a serial bridge controller coupled to said system clock;
a serial bus memory coupled to said SPI clock;
a host serial interface coupled to said serial bus memory and configured to be switchable between an active state and an inactive state; and
an SPI slave controller coupled to said serial bus memory, said host serial interface, and said SPI clock and configured to
generate a request active signal based upon a request for a transaction from the host processor, the request active signal causing each of said system clock, said SPI clock, and said host serial interface into the active state,
store, based upon the request active signal, data corresponding to the request for the transaction from the host processor to the MCU in said serial bus memory, and
switch said host serial interface to the inactive state based upon the data corresponding to the request for the transaction being stored, said serial bridge controller configured to
process the request for the transaction based upon the request active signal, and
generate a request complete signal based upon the request for the transaction being processed, said SPI slave controller configured to switch the system clock to the inactive state based upon the request complete signal, said SPI clock being switched to the inactive state based upon the request complete signal.
2. The electronic device of claim 1 wherein said SPI clock is switched to the inactive state based upon there being no further request for a transaction from the host processor.
3. The electronic device of claim 1 wherein said serial bridge controller comprises a plurality of sequential logic circuits coupled together and configured to generate the request complete signal based upon the request active signal and the system clock.
4. The electronic device of claim 1 wherein said serial bridge controller comprises delay circuitry configured to cooperate with said SPI slave controller to delay switching the system clock to the inactive state.
5. The electronic device of claim 4 wherein said delay circuitry comprises a system clock divider and a delay counter coupled thereto.
6. The electronic device of claim 5 wherein said system clock divider comprises a divide by X system clock divider, wherein X is a delay of the switching of the system clock to the inactive state in terms of system clock cycles.
7. The electronic device of claim 4 wherein the delay circuitry is configured to delay switching the system clock to the inactive state by a delay of greater than two clock cycles of said system clock.
8. The electronic device of claim 1 wherein said SPI slave controller comprises a plurality of sequential logic circuits coupled together.
9. The electronic device of claim 1 wherein said serial bridge controller is configured to process the request for the transaction based upon reading the request for the transaction from said serial bus memory.
10. An electronic device for communicating between a microcontroller unit (MCU) and a host processor, the electronic device comprising:
a system clock configured to be switchable between an active state and an inactive state;
an SPI clock configured to be switchable between an active state and an inactive state;
a serial bridge controller coupled to said system clock;
a serial bus memory coupled to said SPI clock;
a host serial interface coupled to said serial bus
memory and configured to be switchable between an active state and an inactive state; and
an SPI slave controller coupled to said serial bus memory, said host serial interface, and said SPI clock and configured to
generate a request active signal based upon a request for a transaction from the host processor, the request active signal causing each of said system clock, said SPI clock, and said host serial interface into the active state,
store, based upon the request active signal, data corresponding to the request for the transaction from the host processor to the MCU in said serial bus memory, and
switch said host serial interface to the inactive state based upon the data corresponding to the request for the transaction being stored, said serial bridge controller configured to
process the request for the transaction based upon the request active signal based upon reading the request for the transaction from said serial bus memory,
generate a request complete signal based upon the request for the transaction being processed, and
process the request for the transaction said SPI slave controller configured to switch the system clock to the inactive state based upon the request complete signal, said SPI clock being switched to the inactive state based upon the request complete signal and there being no further request for a transaction from the host processor.
11. The electronic device of claim 10 wherein said serial bridge controller comprises a plurality of sequential logic circuits coupled together and configured to generate the request complete signal based upon the request active signal and the system clock.
12. The electronic device of claim 10 wherein said serial bridge controller comprises delay circuitry configured to cooperate with said SPI slave controller to delay switching the system clock to the inactive state.
13. The electronic device of claim 12 wherein said delay circuitry comprises a system clock divider and a delay counter coupled thereto.
14. The electronic device of claim 13 wherein said system clock divider comprises a divide by X system clock divider, wherein X is a delay of the switching of the system clock to the inactive state in terms of system clock cycles.
15. The electronic device of claim 12 wherein the delay circuitry is configured to delay switching the system clock to the inactive state by a delay of greater than two clock cycles of said system clock.
16. The electronic device of claim 10 wherein said SPI slave controller comprises a plurality of sequential logic circuits coupled together.
17. A method of communicating between a microcontroller unit (MCU) and a host processor, the method comprising:
using a serial peripheral interface (SPI) slave controller coupled to a serial bus memory, a host serial interface, and an SPI clock coupled to the serial bus memory to
generate a request active signal based upon a request for a transaction from the host processor, the request active signal causing each of a system clock coupled to a serial bridge controller, the SPI clock, and the host serial interface into an active state,
store, based upon the request active signal, data corresponding to the request for the transaction from the host processor to the MCU in the serial bus memory, and
switch the host serial interface to an inactive state based upon the data corresponding to the request for the transaction being stored; and
using the serial bridge controller to
process the request for the transaction based upon the request active signal, and
generate a request complete signal based upon the request for the transaction being processed, the SPI slave controller being further used to switch the system clock to the inactive state based upon the request complete signal, the SPI clock being switched to the inactive state based upon the request complete signal.
18. The method of claim 17 wherein using the SPI clock is switched to the inactive state based upon there being no further request for a transaction from the host processor.
19. The method of claim 17 wherein using the serial bridge controller comprises using a plurality of sequential logic circuits coupled together to generate the request complete signal based upon the request active signal and the system clock using.
20. The method of claim 17 wherein the using the serial bridge controller comprises using delay circuitry to cooperate with the SPI slave controller to delay switching the system clock to the inactive state.