Semiconductor film, transistor, semiconductor device, display device, and electronic appliance

1. An oxide semiconductor layer,

wherein the oxide semiconductor layer has a plurality of electron diffraction patterns, which are observed in such a manner that a surface where the oxide semiconductor layer is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the oxide semiconductor layer and the position of the electron beam are relatively moved,

wherein the plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas,

wherein the plurality of electron diffraction patterns are oriented randomly,

wherein a sum of a percentage of first electron diffraction patterns and a percentage of second electron diffraction patterns accounts for 100% of the 50 or more electron diffraction patterns,

wherein the first electron diffraction patterns account for 90% or more of the 50 or more electron diffraction patterns,

wherein the first electron diffraction patterns include observed points which indicate that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor layer is formed, and

wherein the second electron diffraction patterns include observed points that are not symmetry or an observed region disposed in a ring shape.

2. The oxide semiconductor layer according to claim 1 , wherein a region in which one of the second electron diffraction patterns is observed includes a nanocrystal.

3. The oxide semiconductor layer according to claim 1 ,

wherein the oxide semiconductor layer comprises In, an element M, and Zn,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn of the oxide semiconductor layer satisfies In:M:Zn=x:y:z, and

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=2:2:1), second coordinates (x:y:z=23:27:25), third coordinates (x:y:z=8:12:35), fourth coordinates (x:y:z=4:0:7), fifth coordinates (x:y:z=2:0:3), sixth coordinates (x:y:z=7:1:8), seventh coordinates (x:y:z=10:4:7), and the first coordinates, in this order.

4. The oxide semiconductor layer according to claim 1 ,

wherein the oxide semiconductor layer is formed by a sputtering method using a target including In, an element M, and Zn,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn of the target satisfies In:M:Zn=a:b:c, and

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (a:b:c=2:2:1), second coordinates (a:b:c=23:27:25), third coordinates (a:b:c=1:2:9), fourth coordinates (a:b:c=1:0:3), fifth coordinates (a:b:c=2:0:3), sixth coordinates (a:b:c=7:1:8), seventh coordinates (a:b:c=10:4:7), and the first coordinates, in this order.

5. A transistor comprising the oxide semiconductor layer according to claim 1 in a channel region.

6. A semiconductor device comprising the oxide semiconductor layer according to claim 1 .

7. An oxide semiconductor layer,

wherein the oxide semiconductor layer has a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor layer is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the oxide semiconductor layer and the position of the electron beam are relatively moved,

wherein the plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas,

wherein first electron diffraction patterns account for 100% of the 50 or more electron diffraction patterns,

wherein the first electron diffraction patterns include observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor layer is formed, and

wherein the plurality of electron diffraction patterns are oriented randomly.

8. A semiconductor device comprising: an oxide semiconductor layer comprising In, an element M, and Zn; and

an insulating later that contains oxygen in excess of the stoichiometric compostion,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein the oxide semiconductor layer inculdes a plurality of crystals,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn satisfies In:M:Zn=x:y:z, and

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=2:2:1), second coordinates (x:y:z=23:27:25), third coordinates (x:y:z=8:12:35), fourth coordinates (x:y:z=4:0:7), fifth coordinates (x:y:z=2:0:3), sixth coordinates (x:y:z=7:1:8), seventh coordinates (x:y:z=10:4:7), and the first coordinates, in this order.

9. A transistor comprising the oxide semiconductor layer according to claim 8 in a channel region.

10. A semiconductor device comprising: an oxide semiconductor layer comprising In, Ga, and Zn; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein the oxide semiconductor layer includes a pluraloty of crystals,

wherein an atomic ratio of In to Ga and Zn satisfies In:Ga:Zn=x:y:z, and

wherein, in an equilibrium diagram with vertices of the three elements of In, Ga, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=2:2:1), second coordinates (x:y:z=23:27:25), third coordinates (x:y:z=8:12:35), fourth coordinates (x:y:z=4:0:7), fifth coordinates (x:y:z=2:0:3), sixth coordinates (x:y:z=7:1:8), seventh coordinates (x:y:z=10:4:7), and the first coordinates, in this order.

11. A transistor comprising the oxide semiconductor layer according to claim 10 in a channel region.

12. The semiconductor device according to claim 10 , further comprising:

a second oxide layer; and

a third oxide layer,

wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and

wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

13. The semiconductor device according to claim 12 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

14. The semiconductor device according to claim 12 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

15. A semiconductor device comprising:

a first oxide layer;

a second oxide layer; and

an insulating layer that contains oxygen in excess of the stoichiometric compostion,

wherein the insulating layer and the second oxide layer overlap each other,

wherein the second oxide layer includes a plurality of crystals,

wherein the second oxide layer includes a region in contact with the first oxide layer,

wherein the first oxide layer includes a first portion,

wherein the second oxide layer includes a second portion,

wherein the first portion includes In, an element M, and Zn,

wherein an atomic ratio of In to the element M and Zn of the first portion satisfies In:M:Zn=x a :y a :z a , and

wherein x a , y a , z a , and α satisfy one of the following conditions:

x a :y a :z a =(1−α):(1+α):1 and −0.33≦α≦+0.08;

x a :y a :z a =(1−α):(1+α):2 and −0.68≦α≦+0.32;

x a :y a :z a =(1−α):(1+α):3 and −1≦α≦+0.46;

x a :y a :z a =(1−α):(1+α):4 and −1≦α≦+0.54; and

x a :y a :z a =(1−α):(1+α):5 and −1≦α≦+0.72.

16. The semiconductor device according to claim 15 , wherein the x b and the y b satisfy x b >y b .

17. The semiconductor device according to claim 15 , wherein electron affinity of the first portion is smaller than electron affinity of the second portion.

18. The semiconductor device according to claim 15 , further comprising a third oxide layer,

wherein the third oxide layer includes a region in contact with the second oxide film,

wherein the third oxide layer includes a third portion, and

wherein electron affinity of the third portion is smaller than electron affinity of the second portion.

19. A display device comprising the semiconductor device according to claim 15 , the display device further comprising a display element.

20. An electronic appliance comprising the display device according to claim 15 , the electronic appliance further comprising a microphone, a speaker, or an operation key.

21. An electronic appliance comprising the semiconductor device according to claim 19 , the electronic appliance further comprising a microphone, a speaker, or an operation key.

22. A semiconductor device comprising:

a first oxide layer; and

a second oxide layer; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the second oxide layer overlap each other,

wherein the second oxide layer includes a plurality of crystals,

wherein the second oxide layer includes a region in contact with the first oxide layer,

wherein the first oxide layer includes a first portion,

wherein the second oxide layer includes a second portion,

wherein the first portion includes In, an element M, and Zn,

wherein a first atomic ratio of In to the element M and Zn of the first portion satisfies In:M:Zn=x a :y a :z a ,

wherein the second oxide layer includes In, the element M, and Zn,

wherein a second atomic ratio of In to the element M and Zn of the second oxide layer satisfies In:M:Zn=x b :y b :z b ,

wherein in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the first atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x a :y a :z a =8:14:7), second coordinates (x a :y a :z a =2:5:7), third coordinates (x a :y a :z a =51:149:300), fourth coordinates (x a :y a :z a =46:288:833), fifth coordinates (x a :y a :z a =0:2:11), sixth coordinates (x a :y a :z a =0:0:1), seventh coordinates (x a :y a :z a =2:2:1), and the first coordinates, in this order, and

wherein in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the second atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x b :y b :z b =2:2:1), second coordinates (x b :y b :z b =23:27:25), third coordinates (x b :y b :z b =8:12:35), fourth coordinates (x b :y b :z b =4:0:7), fifth coordinates (x b :y b :z b =2:0:3), sixth coordinates (x b :y b :z b =7:1:8), seventh coordinates (x b :y b :z b =10:4:7), and the first coordinates, in this order.

23. The semiconductor device according to claim 22 , further comprising a first transistor,

wherein the second oxide layer functions as a channel region of the first transistor.

24. The semiconductor device according to claim 2 ,

wherein one of the following conditions is satisfied:

x a :y a :z a =(1−α):(1+α):1 and −0.33≦α≦+0.08;

x a :y a :z a =(1−α):(1+α):2 and −0.68≦α≦+0.32;

x a :y a :z a =(1−α):(1+α):3 and −1≦α≦+0.46;

x a :y a :z a =(1−α):(1+α):4 and −1≦α≦+0.54; and

x a :y a :z a =(1−α):(1+α):5 and −1≦α≦+0.72.

25. The semiconductor device according to claim 24 ,

wherein one of the following conditions is satisfied:

x b :y b :z b =(1−β):(1+β):1 and −0.33≦β≦+0.08;

x b :y b :z b =(1−β):(1+β):2 and −0.68≦β≦+0.32;

x b :y b :z b =(1−β):(1+β):3 and −1≦β≦+0.46;

x b :y b :z b =(1−β):(1+β):4 and −1≦β≦+0.54; and

x b :y b :z b =(1−β):(1+β):5 and −1≦β≦+0.72.

26. The semiconductor device comprising: an oxide semiconductor layer comprising In, an element M, and Zn; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein the oxide semiconductor layer includes a plurality of crystals,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn satisfies In:M:Zn=x:y:z, and

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=2:2:1), second coordinates (x:y:z=23:27:25), third coordinates (x:y:z=8:12:35), fourth coordinates (x:y:z=4:0:7), fifth coordinates (x:y:z=2:0:3), sixth coordinates (x:y:z=7:1:8), seventh coordinates (x:y:z=15:5:8), and the first coordinates, in this order.

27. A transistor comprising the oxide semiconductor layer according to claim 26 in a channel region.

28. A semiconductor device comprising: an oxide semiconductor layer comprising In, an element M, and Zn; and

an insulating layer that contains oxygen in excess of the stoichiometric composition,

wherein the insulating layer and the oxide semiconductor layer overlap each other,

wherein the oxide semiconductor layer includes a plurality of crystals,

wherein the element M is at least one of aluminum, gallium, yttrium, and tin,

wherein an atomic ratio of In to the element M and Zn satisfies In:M:Zn=x:y:z, and

wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=8:14:7), second coordinates (x:y:z=2:5:7), third coordinates (x:y:z=51:149:300), fourth coordinates (x:y:z=46:288:833), fifth coordinates (x:y:z=0:2:11), sixth coordinates (x:y:z=0:0:1), seventh coordinates (x:y:z=1:0:0), and the first coordinates, in this order.

29. A transistor comprising the oxide semiconductor layer according to claim 28 in a channel region.