Architecture for 3-D NAND memory
View Patent ↗Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
1. An apparatus, comprising:
a plurality of stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked on top of the first array;
a data plate associated with multiple rows of memory cell strings of at least one of the plurality of stacked memory arrays; and
for each of the memory cell strings associated with the data plate, a plurality of select gates coupled between a memory cell region of the memory cell string and the data plate,
wherein the plurality of select gates includes a first select gate to select a respective row of blocks, wherein a block in the respective row of blocks includes a memory cell string from the first array and a memory cell string from the second array, wherein the data plate is located between the first array and the second array and shared by all of the memory cell strings in the first array and the second array, and wherein the memory cell strings are vertically aligned with a vertical axis of the plurality of stacked memory arrays.
2. The apparatus of claim 1 , wherein the memory cell strings include NAND memory cell strings.
3. The apparatus of claim 1 , wherein each of the memory cell strings includes a memory cell region, with a drain select gate disposed between the memory cell region and a data line to which the memory cell string is coupled.
4. The apparatus of claim 3 , wherein the drain select gate comprises a plurality of hierarchical select gates coupled between the memory cell region of the memory cell string and the data line to which the memory cell string is coupled.
5. The apparatus of claim 1 , wherein each of the memory cell strings includes a source select gate disposed between a memory cell region and a source to which the memory cell string is coupled.