IP Library Granted Patent US 10,438,928
Granted Patent B2
US 10,438,928 · App. 14/626,575 · Granted Oct 8, 2019

Apparatuses and methods for semiconductor die heat dissipation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,438,928
App. No.
14/626,575
Granted
Oct 8, 2019
Kind
B2
Abstract

Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

Claims (42)

1. An apparatus, comprising:

a substrate;

a thermal interface layer disposed on a surface of the substrate; and

a heat spreader including a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer, and

wherein the heat spreader including the plurality of substrate-facing protrusions covers an entire surface of a top die of a stack of semiconductor die.

2. The apparatus of claim 1 , wherein the plurality of substrate-facing protrusions are disposed through the thermal interface layer and are in contact with the substrate.

3. The apparatus of claim 1 , wherein a subset of the plurality of substrate-facing protrusions are disposed through the thermal interface layer and are in contact with the substrate.

4. The apparatus of claim 1 , wherein a thickness of the thermal interface layer under a face of the plurality of substrate-facing protrusions facing the substrate is thinner relative to a thickness of the thermal interface layer under areas of the heat spreader that have no substrate-facing protrusions.

5. The apparatus of claim 1 , wherein the plurality of substrate-facing protrusions form an array of protrusions.

6. The apparatus of claim 1 , wherein the substrate further includes a plurality of thermal dissipation pads, and wherein a substrate-facing protrusion of the plurality of substrate-facing protrusions is in contact with one or more of the plurality of thermal dissipation pads.

7. The apparatus of claim 1 , wherein the plurality of substrate-facing protrusions are disposed through the thermal interface layer and are in substantially close proximity with the substrate with a small volume of the thermal interface layer between a bottom face of each of the plurality of substrate-facing protrusions and the substrate.

8. The apparatus of claim 1 , wherein the substrate is a semiconductor die.

9. The apparatus of claim 8 , wherein the semiconductor die is a memory die.

10. The apparatus of claim 1 , wherein the plurality of substrate-facing protrusions extend from the heat spreader, and the heat spreader covers the terminal interface layer.

11. An apparatus, comprising:

a substrate,

a semiconductor die on the substrate;

a plurality of thermal dissipation pads on a surface of the substrate and the semiconductor die;

a thermal interface layer disposed on the surface of the substrate that includes the plurality of thermal dissipation pads; and

a heat spreader including a plurality of internally-facing protrusions associated with one stack of the semiconductor die, wherein a distal end of the plurality of internal-facing protrusions are at least partially disposed within the thermal interface layer,

wherein the distal end of an internally-facing protrusion of the plurality of internally-facing protrusions is in contact with a thermal dissipation pad on the semiconductor die of the plurality of thermal dissipation pads, and

wherein the plurality of internally-facing protrusions associated with the one stack of the semiconductor die are part of, and are formed of, a same material as the heat spreader.

12. The apparatus of claim 11 , wherein the plurality of thermal dissipation pads and the plurality of internally-facing protrusions are aligned.

13. The apparatus of claim 11 , wherein the plurality of thermal dissipation pads are arranged in an array on the surface of the substrate.

14. The apparatus of claim 11 , wherein the plurality of thermal dissipation pads includes a through-via bonding pad.

15. The apparatus of claim 14 , wherein the plurality of internally-facing protrusions form an array and spaces between a subset of the plurality of internally-facing protrusions align with a through-via bonding pad.

16. The apparatus of claim 11 , wherein a eutectic bond is formed between one or more of the plurality of internally-facing protrusions and one or more of the plurality of thermal dissipation pads.

17. The apparatus of claim 11 , wherein a bottom die of the stack of semiconductor die extends beyond one or more of the other die in the stack of semiconductor die and includes an exposed portion.

18. The apparatus of claim 17 , wherein the exposed portion of the bottom die includes a plurality of thermal dissipation pads, and wherein one or more of the internally-facing protrusions are in close proximity to or in contact with the exposed portion of the bottom die including one or more of the plurality of thermal dissipation pads.

19. The apparatus of claim 10 , wherein the internally-facing protrusions part of, and formed of, the same material as the heat spreader are disposed above the one stack of the semiconductor die.

20. An apparatus, comprising:

a heat spreader including a plurality of protrusions formed on a bottom side of the heat spreader;

a stack of semiconductor die including a top die;

a thermal interface layer disposed between a surface of the top die and the bottom side of the heat spreader; and

a plurality of thermal dissipation pads on the surface of the top die,

wherein the heat spreader is disposed on the top die with the thermal interface layer between the bottom side of the heat spreader and the surface of the top die,

wherein the plurality of protrusions imbedded, at least partially, into the thermal interface layer are in contact with at least one of the plurality of thermal dissipation pads, and

wherein a bottom die of the stack of semiconductor die extends beyond one or more of other die in the stack of semiconductor die and a top surface of each exposed portion of the bottom die includes a plurality of thermal dissipation pads separated by corresponding portions of a thermal interface layer.

21. The apparatus of claim 20 , wherein one or more of the plurality of protrusions extend through the thermal interface layer and are in contact with the surface of the top die.

22. The apparatus of claim 20 , wherein one or more of the plurality of protrusions are in contact with one or more of the plurality of thermal dissipation pads.

23. The apparatus of claim 20 , wherein the heat spreader comprises a conformal lid.

24. The apparatus of claim 23 , wherein the hea spreader forms part of a package for the stack of semiconductor die.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2015
From: VADHAVKAR, SAMEER S.; LI, XIAO; CHANDOLU, ANILKUMAR
To: MICRON TECHNOLOGY, INC.
Reel/Frame 034988/0258 →