Mapping of algorithms to neurosynaptic hardware
One embodiment of the invention provides a method comprising defining a brainlet representing a platform-agnostic network of neurons, synapses, and axons. The method further comprises compiling the brainlet into a corelet for mapping onto neurosynaptic substrate, and mapping the corelet onto the neurosynaptic substrate. The corelet is compatible with one or more conditions related to the neurosynaptic substrate.
1. A method, comprising:
defining a first software abstraction representing a neural network of neurons, synapses, and axons, wherein the first software abstraction comprises an imperative program for an algorithm;
compiling the first software abstraction into a second software abstraction for mapping onto a neurosynaptic hardware, wherein the second software abstraction is compatible with one or more conditions related to the neurosynaptic hardware, the conditions comprises at least one of a hardware-specific constraint related to the neurosynaptic hardware and a performance constraint, and the second software abstraction comprises a hardware-specific program for the algorithm; and
mapping the second software abstraction onto the neurosynaptic hardware, such that the neurosynaptic hardware simulates the neural network based on the algorithm.
2. The method of claim 1 , further comprising:
compiling the first software abstraction for simulation; and
simulating the first software abstraction to evaluate performance on task.
3. The method of claim 2 , further comprising:
relaxing one or more of the conditions based on the performance;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
4. The method of claim 2 , further comprising:
restoring one or more of the conditions based on the performance;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
5. The method of claim 2 , further comprising:
running one or more portions of the first software abstraction on different execution engines.
6. The method of claim 1 , wherein the neurosynaptic hardware comprises one or more interconnected cores, and each core comprises a plurality of electronic neurons, a plurality of electronic axons, and a plurality of synapses interconnecting the neurons to the axons.
7. The method of claim 2 , wherein:
the first software abstraction is constrained based on the conditions.
8. The method of claim 7 , further comprising:
trading one or more hardware-specific constraints related to the neurosynaptic hardware with one or more performance constraints;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
9. A system, comprising:
at least one processor; and
a non-transitory processor-readable memory device storing instructions that when executed by the at least one processor causes the at least one processor to perform operations including:
defining a first software abstraction representing a neural network of neurons, synapses, and axons, wherein the first software abstraction comprises an imperative program for an algorithm;
compiling the first software abstraction into a second software abstraction for mapping onto a neurosynaptic hardware, wherein the second software abstraction is compatible with one or more conditions related to the neurosynaptic hardware, the conditions comprises at least one of a hardware-specific constraint related to the neurosynaptic hardware and a performance constraint, and the second software abstraction comprises a hardware-specific program for the algorithm; and
mapping the second software abstraction onto the neurosynaptic hardware, such that the neurosynaptic hardware simulates the neural network based on the algorithm.
10. The system of claim 9 , wherein the operations further include:
compiling the first software abstraction for simulation; and
simulating the first software abstraction to evaluate performance on task.
11. The system of claim 10 , wherein the operations further include:
relaxing one or more of the conditions based on the performance;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
12. The system of claim 10 , wherein the operations further include:
restoring one or more of the conditions based on the performance;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
13. The system of claim 10 , wherein the operations further include:
running one or more portions of the first software abstraction on different execution engines.
14. The system of claim 10 , wherein the neurosynaptic hardware comprises one or more interconnected cores, and each core comprises a plurality of electronic neurons, a plurality of electronic axons, and a plurality of synapses interconnecting the neurons to the axons.
15. The system of claim 10 , wherein:
the first software abstraction is constrained based on the conditions.
16. The system of claim 15 , wherein the operations further include:
trading one or more hardware-specific constraints related to the neurosynaptic hardware with one or more performance constraints;
re-compiling the first software abstraction for simulation; and
re-simulating the first software abstraction to re-evaluate performance on task.
17. The system of claim 9 , wherein the first software abstraction is
defined via one of the following programming interfaces: a text editor, or a visual programmer.
18. The system of claim 9 , wherein the system is an integrated development environment.
19. The system of claim 9 , wherein one or more portions of the first software abstraction may run on different platforms.
20. A non-transitory computer program product, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:
define a first software abstraction representing a neural network of neurons, synapses, and axons, wherein the first software abstraction comprises an imperative program for an algorithm;
compile the first software abstraction into a second software abstraction for mapping onto a neurosynaptic hardware, wherein the second software abstraction is compatible with one or more conditions related to the neurosynaptic hardware, the conditions comprises at least one of a hardware-specific constraint related to the neurosynaptic hardware and a performance constraint, and the second software abstraction comprises a hardware-specific program for the algorithm; and
map the second software abstraction onto the neurosynaptic hardware, such that the neurosynaptic hardware simulates the neural network based on the algorithm.