Display device having shared column lines
A display device having at least a plurality of pixel circuits, connected to signal lines to which data signals in accordance with luminance information are supplied, arranged in a matrix, wherein pixel circuits of odd number columns and even number columns adjacent sandwiching an axis in a column direction parallel to an arrangement direction of the signal lines have a mirror type circuit arrangement symmetric about the axis of the column direction, and there are lines different from the signal lines between signal lines of adjacent pixel circuits.
1. A display device comprising:
a plurality of pixel circuits arranged in a matrix;
a set of first potential lines, which are arranged in a same direction as an arrangement direction of a set of signal lines, where first ends of each line of the set of first potential lines are connected to a first common line, and where second ends of each line of the set of first potential lines are connected to a second common line
a plurality of second potential lines;
a plurality of signal lines; and
a control unit;
wherein a given one of the pixel circuits includes:
a light emitting element,
a capacitor,
a first transistor connected to a current path between one of the plurality of first potential lines and the light emitting element, and configured to control a magnitude of a driving current supplied to the light emitting element,
a second transistor connected to the current path between the one of the plurality of first potential lines and the light emitting element and configured as a switch,
a third transistor connected to a signal path extending between one of the plurality of signal lines and the capacitor and configured to supply a data voltage from the one of the plurality of signal lines to the capacitor when in a conductive state, and
a fourth transistor connected to one of the plurality of second potential lines and configured to supply a potential of the one of the plurality of second potential lines to a gate of the first transistor when in a conductive state;
wherein the control unit is configured to cause, during a given one field period, in order:
the fourth transistor to be in a conductive state such that a second potential is supplied to the gate of the first transistor,
the third transistor to be in a conductive state such that the gate potential of the first transistor becomes a display potential whose magnitude depends on the data voltage and on a threshold value of the first transistor, and
the second transistor to be in a conductive state such that the drive current is supplied from the first transistor to the light emitting element, and
wherein one of the plurality of the second potential lines is connected to:
the given one of the pixel circuits, and
another one of the pixel circuits that is adjacent to the given one of the pixel circuits.
2. The display device of claim 1 , wherein the one of the plurality of the second potential lines that is disposed adjacent to the one of the plurality of the signal lines connected to the given one of the pixel circuits is also connected to the given one of the pixel circuits.
3. The display device of claim 1 , wherein the one of the plurality of the second potential lines and the one of the plurality of the signal lines connected to the given one of the pixel circuits are adjacent to each other with no transistor being disposed therebetween.
4. The display device of claim 1 , wherein the upper ends and lower ends of each of the plurality of first potential lines are connected to common lines out of the display region.
5. The display device of claim 1 , wherein each of the plurality of the signal lines is connected to a selection switch such that the control circuit supplies the data voltage to the plurality of the signal lines in the time division manner.
6. The display device of claim 1 ,
wherein pixel circuits of an odd number column and an even number column adjacent to each other and sandwiching an axis in a column direction therebetween have a mirror type circuit arrangement symmetric with respect to the axis in the column direction.
7. The display device of claim 6 ,
wherein the axis is corresponding to one of the second potential lines.
8. The display device of claim 1 ,
wherein pixel circuits of an odd number column and an even number column adjacent to each other are disposed so as to sandwich one of the second potential lines connected to the pixel circuits of the odd number column and the even number column.
9. The display device of claim 1 ,
wherein least the first transistor is configured by p-channel TFT.
10. The display device of claim 1 ,
wherein the first transistor, the second transistor, the third transistor and the forth transistor are configured by p-channel TFTs.