Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods
Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.
1. A memory system for a processor-based system, comprising:
a memory;
a memory controller configured to:
periodically power-up during idle periods of a processor;
generate a power-up signal indicating a powered-up state of the memory controller;
respond to requests from the processor to perform memory transactions to the memory in response to the powered-up state; and
generate the power-up signal indicating a powered-down state of the memory controller in response to an idle period of the processor; and
a memory data scrubber circuit configured to:
receive the power-up signal from the memory controller; and
perform a memory data scrubbing operation on at least one next scrubbing memory address in the memory in response to receiving the power-up signal from the memory controller and independent of the powered-down state of the memory controller.
2. The memory system of claim 1 , wherein the memory controller is configured to periodically power-up during the idle periods of the processor to receive at least one memory access request to the memory.
3. The memory system of claim 1 , wherein the memory data scrubber circuit is not provided in the memory controller.
4. The memory system of claim 1 , wherein the memory data scrubber circuit is provided in the memory.
5. The memory system of claim 1 , wherein:
the memory controller is configured generate the powered-up state in the power-up signal in response to the memory controller powering up after the idle period of the processor; and
the memory data scrubber circuit is configured to initiate the performance of the memory data scrubbing operation on the at least one next scrubbing memory address in the memory in response to receiving the power-up signal indicating the powered-up state of the memory controller.
6. The memory system of claim 1 , wherein the memory data scrubber circuit is further configured to:
determine if at least one memory address of at least one memory access request comprising at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
perform the memory data scrubbing operation on the at least one next scrubbing memory address if the at least one memory address of the at least one write operation does not match the at least one next scrubbing memory address in the memory.
7. The memory system of claim 6 , wherein the memory data scrubber circuit is further configured to:
determine if the at least one memory address of the at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
if the at least one memory address of the at least one write operation matches the at least one next scrubbing memory address, not perform the memory data scrubbing operation on the at least one next scrubbing memory address in the memory.
8. The memory system of claim 7 , wherein if the at least one memory address of the at least one write operation matches the at least one next scrubbing memory address, the memory controller is further configured to perform the at least one write operation on the at least one next scrubbing memory address in the memory.
9. The memory system of claim 1 , wherein:
the memory controller is configured to generate the powered-down state in the power-up signal in response to the memory controller powering down after the idle period of the processor; and
the memory data scrubber circuit is configured to perform the memory data scrubbing operation on the at least one next scrubbing memory address in the memory after the received power-up signal indicates the powered-down state of the memory controller.
10. The memory system of claim 1 , wherein the memory data scrubber circuit is further configured to set the at least one next scrubbing memory address to at least one memory address of at least one memory access request comprising at least one read operation if at least one read data for the at least one read operation contains an error.
11. The memory system of claim 10 , wherein the memory data scrubber circuit is further configured to:
determine if the at least one memory address of the at least one read operation having the at least one read data containing the error matches the at least one memory address of the at least one memory access request comprising at least one write operation; and
if the at least one memory address of the at least one read operation having the at least one read data containing the error matches the at least one memory address of the at least one memory access request comprising the at least one write operation from the memory controller, not perform the memory data scrubbing operation on the at least one memory address of the at least one read operation having the at least one read data containing the error.
12. The memory system of claim 10 , wherein the memory data scrubber circuit is further configured to:
determine if the at least one memory address of the at least one memory access request further comprising at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
perform the memory data scrubbing operation on the at least one next scrubbing memory address if the at least one memory address of the at least one write operation does not match the at least one next scrubbing memory address in the memory.
13. The memory system of claim 12 , wherein the memory data scrubber circuit is further configured to:
determine if the at least one memory address of the at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
if the at least one memory address of the at least one write operation matches the at least one next scrubbing memory address, not perform the memory data scrubbing operation on the at least one next scrubbing memory address in the memory.
14. The memory system of claim 12 , wherein the memory data scrubber circuit is configured to perform the memory data scrubbing operation on the at least one next scrubbing memory address in the memory after the received power-up signal indicates the powered-down state of the memory controller.
15. The memory system of claim 1 , wherein the memory data scrubber circuit is further configured to:
verify the memory data scrubbing operation performed on memory data in the at least one next scrubbing memory address failed; and
remap the at least one next scrubbing memory address to at least one new memory address in the memory if verification of the memory data scrubbing operation performed on the memory data in the at least one next scrubbing memory address failed.
16. The memory system of claim 1 , wherein the memory data scrubber circuit is further configured to:
determine the at least one next scrubbing memory address in the memory to be data scrubbed; and
store the determined at least one next scrubbing memory address as the at least one next scrubbing memory address.
17. The memory system of claim 1 , wherein the memory is comprised of magnetic random access memory (MRAM).
18. The memory system of claim 1 integrated into an integrated circuit (IC).
19. The memory system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.
20. A memory system for a processor-based system, comprising:
a means for storing data;
a means for controlling configured for:
periodically powering-up during idle periods of a processor;
generating a power-up signal indicating a powered-up state of the means for controlling;
responding to requests from the processor to perform memory transactions to the means for storing data in response to the powered-up state; and
generating the power-up signal indicating a powered-down state of the means for controlling in response to an idle period of the processor; and
a means for scrubbing configured for:
receiving the power-up signal from the means for controlling; and
performing a memory data scrubbing operation on at least one next scrubbing memory address in the means for storing data in response to receiving the power-up signal from the means for controlling and independent of the powered-down state of the means for controlling.
21. A method for scrubbing memory data in a memory of a memory system for a processor-based system, comprising:
receiving a power-up signal from a memory controller indicating a powered-up state of the memory controller in response to the memory controller waking-up during an idle period of a processor;
responding to requests from the processor to perform memory transactions to the memory in response to the powered-up state;
receiving the power-up signal indicating a powered-down state of the memory controller in response to the idle period of the processor; and
performing a memory data scrubbing operation on at least one next scrubbing memory address in the memory in response to the received power-up signal from the memory controller and independent of the powered-down state of the memory controller.
22. The method of claim 21 , comprising starting the performance of the memory data scrubbing operation on the at least one next scrubbing memory address in the memory in response to receiving the power-up signal indicating the powered-up state of the memory controller.
23. The method of claim 21 , further comprising:
determining if at least one memory address of at least one memory access request comprising at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
performing the memory data scrubbing operation on the at least one next scrubbing memory address if the at least one memory address of the at least one write operation does not match the at least one next scrubbing memory address in the memory.
24. The method of claim 23 , further comprising:
determining if the at least one memory address of the at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
if the at least one memory address of the at least one write operation matches the at least one next scrubbing memory address, not performing the memory data scrubbing operation on the at least one next scrubbing memory address in the memory.
25. The method of claim 21 , comprising performing the memory data scrubbing operation on the at least one next scrubbing memory address in the memory in response to receiving the power-up signal indicating the powered-down state of the memory controller.
26. The method of claim 21 , further comprising setting the at least one next scrubbing memory address to at least one memory address of at least one memory access request comprising at least one read operation if at least one read data for the at least one read operation contains an error.
27. The method of claim 26 , further comprising:
determining if the at least one memory address of the at least one read operation having the at least one read data containing the error matches the at least one memory address of the at least one memory access request comprising at least one write operation; and
if the at least one memory address of the at least one read operation having the at least one read data containing the error matches the at least one memory address of the at least one memory access request comprising the at least one write operation from the memory controller, not performing the memory data scrubbing operation on the at least one memory address of the at least one read operation having the at least one read data containing the error.
28. The method of claim 26 , further comprising:
determining if the at least one memory address of the at least one memory access request further comprising at least one write operation from the memory controller matches the at least one next scrubbing memory address; and
performing the memory data scrubbing operation on the at least one next scrubbing memory address if the at least one memory address of the at least one write operation does not match the at least one next scrubbing memory address in the memory.
29. The method of claim 21 , further comprising:
verifying the memory data scrubbing operation performed on memory data in the at least one next scrubbing memory address failed; and
remapping the at least one next scrubbing memory address to at least one new memory address in the memory if verification of the memory data scrubbing operation performed on the memory data in the at least one next scrubbing memory address failed.
30. A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause a memory system for a processor-based system to:
receive a power-up signal from a memory controller indicating a powered-up state of the memory controller in response to the memory controller waking-up during an idle period of the processor;
respond to requests from the processor to perform memory transactions to a memory in response to the powered-up state;
receive the power-up signal indicating a powered-down state of the memory controller in response to the idle period of the processor; and
perform a memory data scrubbing operation on at least one next scrubbing memory address in the memory in response to the received power-up signal indicating the powered-up state of the memory controller and independent of the powered-down state of the memory controller.