Vertical DMOS transistor

1. A method for forming a transistor, comprising:

providing a semiconductor body;

forming a body region of a first conductivity type in the semiconductor body;

forming a gate electrode partially overlapping the body region, the gate electrode being insulated from the semiconductor body by a gate dielectric layer;

forming a source diffusion region of a second conductivity type in the body region on a first side of the gate electrode;

forming a trench in the semiconductor body on a second side, opposite the first side, of the gate electrode;

forming a sidewall dielectric layer lining the sidewall only of the trench without filling the trench; and

implanting dopants of the second conductivity type in the semiconductor body along the sidewall of the trench to form a doped sidewall region in the semiconductor body along the sidewall of the trench, the doped sidewall region forming a vertical drain current path in the semiconductor body adjacent the trench for the transistor.

2. The method of claim 1 , further comprising:

forming a bottom dielectric layer at a lower portion of the trench;

forming a conductive layer in the trench above the bottom dielectric layer; and

electrically connecting the conductive layer to the gate electrode or to the source electrode.

3. The method of claim 1 , wherein providing a semiconductor body comprises:

providing a substrate of the first conductivity type;

forming a buried layer of the second conductivity type on the substrate; and

forming an epitaxial layer of the second conductivity type on the substrate,

wherein the trench reaches at least the buried layer and the drain current of the transistor flows through the doped sidewall region to the buried layer.

4. The method of claim 3 , further comprising:

forming a second trench in the semiconductor body remote from the trench and reaching at least the buried layer;

forming a sidewall dielectric layer in the second trench;

forming a trench bottom doped region of the second conductivity type in the semiconductor body beneath the second trench; and

forming a conductive layer in the second trench,

wherein the conductive layer of the second trench is in electrical contact with the trench bottom doped region and the buried layer, the conductive layer forming a trench drain electrode conducting the drain current of the transistor.

5. The method of claim 1 , further comprising:

forming a trench bottom doped region of the second conductivity type in the semiconductor body beneath the trench and in electrical contact with the doped sidewall region formed in the semiconductor body along the sidewall of the trench;

forming a thick dielectric layer as the sidewall dielectric layer lining the sidewall of the trench; and

forming a conductive layer in the trench in electrical contact with the trench bottom doped region, the conductive layer forming a trench drain electrode,

wherein the drain current of the transistor flowing in the vertical drain current path is directed to the trench bottom doped region and to the trench drain electrode.

6. The method of claim 1 , further comprising:

forming a trench bottom doped region of the second conductivity type in the semiconductor body beneath the trench and in electrical contact with the doped sidewall region formed in the semiconductor body along the sidewall of the trench;

forming a bottom dielectric layer at a lower portion of the trench;

forming a first conductive layer in the trench above the bottom dielectric layer;

etching a first inner trench in the first conductive layer and the bottom dielectric layer;

forming a dielectric layer in the first inner trench;

etching a second inner trench in the dielectric layer to the bottom of the trench;

forming a second conductive layer in the second inner trench in electrical contact with the trench bottom doped region, the remaining dielectric layer insulating the first conductive layer from the second conductive layer, the second conductive layer forming a trench drain electrode;

and

electrically connecting the conductive layer to the gate electrode or to the source electrode,

wherein the drain current of the transistor flowing in the vertical drain current path is directed to the trench bottom doped region and to the trench drain electrode.

7. The method of claim 1 , further comprising:

forming the trench adjacent and next to the second side of the gate electrode without any intervening doped region.