Asynchronous pipelined interconnect architecture with fanout support
Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.
1. A circuit comprising:
a plurality of routing tracks for transmitting data signals in the circuit; and
a multi-port switch point including:
a plurality of ports, each port being connected to a corresponding routing track from the plurality of routing tracks, and
a buffer-switch circuit including:
a buffer circuit;
a plurality of input switch-boxes configured to programmably couple one of the plurality of ports to an input of the buffer circuit;
a plurality of output switch-boxes configured to programmably couple one of the plurality of ports to an output of the buffer circuit; and
a completion detection element configured to combine control signals from control nodes of the ports and to provide a combined control signal at a control node of the output of the buffer circuit, the combined control signal including a combined acknowledge signal for data transmissions of the buffer-switch circuit.
2. The circuit of claim 1 , wherein each port of the multi-port switch point comprises of a plurality of nodes, each node being connected to a wire of a corresponding routing track from the plurality of routing tracks.
3. The circuit of claim 1 , further comprising:
a plurality of logic blocks that comprise an asynchronous circuit, the plurality of logic blocks being interconnected by the plurality of routing tracks.
4. The circuit of claim 1 , wherein the buffer circuit includes an asynchronous buffer circuit that supports pipelining data and control signals.
5. The circuit of claim 1 , wherein the buffer circuit includes a first-in-first-out (FIFO) buffer circuit that supports pipelining data and control signals.
6. The circuit of claim 1 , wherein each of the pluralities of output switch-boxes and input switch-boxes includes transmission gates or transistors.
7. The circuit of claim 1 , wherein the completion detection element is configured to receive acknowledge signals from the control nodes of the ports and to provide the combined acknowledge signal at the control node of the output of the buffer circuit.
8. The circuit of claim 1 , wherein the completion detection element is programmably configured to receive acknowledge signals from a programmable selection of the control nodes of the ports and to provide the combined acknowledge signal at the control node of the output of the buffer circuit.
9. A multi-port switch point for coupling a plurality of logic blocks in a circuit, the multi-port switch point comprising:
a plurality of ports, each port being connected to a corresponding routing track from a plurality of routing tracks that interconnect the plurality of logic blocks, and
a buffer-switch circuit including:
a buffer circuit;
a plurality of input switch-boxes configured to programmably couple one of the plurality of ports to an input of the buffer circuit;
a plurality of output switch-boxes configured to programmably couple one of the plurality of ports to an output of the buffer circuit; and
a completion detection element configured to combine control signals from control nodes of the ports and to provide a combined control signal at a control node of the output of the buffer circuit, the combined control signal including a combined acknowledge signal for data transmissions of the buffer-switch circuit.
10. The multi-port switch point of claim 9 , wherein each port of the multi-port switch point comprises of a plurality of nodes, each node being connected to a wire of a corresponding routing track from the plurality of routing tracks.
11. The multi-port switch point of claim 9 , wherein the plurality of logic blocks comprises an asynchronous circuit.
12. The multi-port switch point of claim 9 , wherein the buffer circuit includes an asynchronous buffer circuit that supports pipelining data and control signals.
13. The multi-port switch point of claim 9 , wherein the buffer circuit includes a first first-in-first-out (FIFO) buffer circuit that supports pipelining data and control signals.
14. The multi-port switch point of claim 9 , wherein each of the pluralities of output switch-boxes and input switch-boxes includes transmission gates or transistors.
15. The multi-port switch point of claim 9 , wherein the completion detection element is configured to receive acknowledge signals from the control nodes of the ports and to provide the combined acknowledge signal at the control node of the output of the buffer circuit.
16. The multi-port switch point of claim 9 , wherein the completion detection element is programmably configured to receive acknowledge signals from a programmable selection of the control nodes of the ports and to provide the combined acknowledge signal at the control node of the output of the buffer circuit.
17. A method comprising:
programmably coupling data nodes of a plurality of ports to an input of a buffer circuit;
programmably coupling an output of the buffer circuit to the data nodes of the plurality of ports;
programmably coupling the data nodes of the plurality of ports to data wires of routing tracks that interconnect plurality of logic blocks; and
combining acknowledge signals from control nodes of the plurality of ports into a combined acknowledge signal for data transmissions between the input of the buffer circuit and the output of the buffer circuit, the combined acknowledge signal being provided to a control node at the output of the buffer circuit.
18. The method of claim 17 , wherein each port of plurality of ports comprises at least one data node, each data node being connected to a data wire of a corresponding routing track from the routing tracks that interconnect the plurality of logic blocks.
19. The method of claim 17 , further comprising:
programmably coupling control nodes corresponding to the data nodes of the plurality of ports to control wires of the routing tracks, the acknowledge signals being combined by accessing the acknowledge signals from the control wires.
20. The method of claim 17 , wherein the acknowledge signals are combined into the single acknowledge signal by a programmable completion detection element that accesses the acknowledge signals from the routing tracks.