Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a molding disposed between the plurality of devices and including a first surface, wherein one of the plurality of devices has substantially different height from another one of the plurality of devices, and the first surface of the molding includes a recessed portion recessed from one of the first surfaces of the plurality of devices.
1. A semiconductor structure, comprising:
a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component;
a molding disposed between the plurality of devices and including a second surface and a third surface opposite to the second surface; and
a metallic shield disposed within the molding and between two of the plurality of devices,
wherein one of the plurality of devices has substantially different height from another one of the plurality of devices, and the second surface of the molding is recessed from and coupled with the first surfaces of the two of the plurality of devices, and the metallic shield is extended from the second surface of the molding to the third surface of the molding.
2. The semiconductor structure of claim 1 , wherein a level of the second surface of the molding is substantially lower than a level of one of the first surfaces of the plurality of devices.
3. The semiconductor structure of claim 1 , wherein the second surface of the molding is substantially greater than about 5 um recessed from one of the first surfaces of the plurality of devices.
4. The semiconductor structure of claim 1 , wherein the plurality of devices include at least one unpackaged device and at least one packaged device.
5. The semiconductor structure of claim 1 , wherein the second surface of the molding is coplanar with a surface of the metallic shield exposed from the molding.
6. The semiconductor structure of claim 1 , further comprising a metallic coating covering the third surface of the molding opposite to the second surface of the molding.
7. The semiconductor structure of claim 1 , further comprising a redistribution layer (RDL) disposed over the first surfaces of the plurality of devices and the second surface of the molding.
8. The semiconductor structure of claim 1 , wherein the plurality of devices include at least one unpackaged device, and the unpackaged device includes a die pad contacted with a redistribution layer (RDL) disposed over the first surfaces of the plurality of devices and the second surface of the molding.
9. The semiconductor structure of claim 1 , wherein the plurality of devices include a bare chip, a ball grid array (BGA) package, a quad flat no leads (QFN) package, a land grid array (LGA) package, a surface mount device (SMD) or a microelectromechanical systems (MEMS) device.
10. A system in package (SiP), comprising:
a plurality of devices;
a molding disposed between the plurality of devices;
a metallic shield disposed within the molding and between two of the plurality of devices; and
a redistribution layer (RDL) disposed over the plurality of devices and the molding,
wherein a first interface between the RDL and the molding is recessed from and coupled with a second interface between the RDL and the plurality of devices, and the metallic shield is extended from the first interface.
11. The system in package of claim 10 , wherein a level of the first interface is substantially greater than about 5 um different from a level of the second interface.
12. The system in package of claim 10 , wherein the plurality of devices are horizontally arranged and supported by the molding.
13. The system in package of claim 10 , wherein the metallic shield is electrically connected to the RDL.
14. A semiconductor structure, comprising:
a metallic layer;
a molding disposed over the metallic layer;
a plurality of devices surrounded by the molding;
a plurality of metallic shields disposed within the molding, contacted with the metallic layer and isolating the plurality of devices from each other;
a redistribution layer (RDL) disposed over the molding, the plurality of devices and the plurality of metallic shields,
wherein the RDL includes a conductive interconnect structure electrically connected with the metallic layer or at least one of the plurality of metallic shields, a first interface between the conductive interconnect structure and one of the plurality of metallic shields is recessed from and coupled with a second interface between the RDL and the plurality of devices.
15. The semiconductor structure of claim 14 , wherein the conductive interconnect structure of the RDL is electrically connected to the plurality of devices.
16. The semiconductor structure of claim 14 , wherein the metallic layer and the plurality of metallic shields define a plurality of compartments for isolating the plurality of devices, and the plurality of devices are disposed within the plurality of compartments respectively.
17. The semiconductor structure of claim 14 , wherein the metallic layer and the plurality of metallic shields include copper, aluminum, lead or solder.
18. The semiconductor structure of claim 14 , further comprising a bond pad disposed over the RDL.
19. The semiconductor structure of claim 14 , wherein each of the plurality of metallic shields is extended orthogonal to the metallic layer.
20. The semiconductor structure of claim 14 , wherein one of the plurality of devices has a height substantially greater or less than a height of another one of the plurality of devices.