Semiconductor structure with TRL and handle wafer cavities
View Patent ↗A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.
1. A method comprising:
fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate, wherein the device layer comprises an active device;
etching the top portion of a handle wafer to form one or more columns in a top portion of the handle wafer;
forming a trap rich layer at the top portion of the handle wafer including at least a portion of interior surfaces of the one or more columns;
bonding a top surface of the handle wafer to a top surface of the semiconductor wafer; and
removing a bottom substrate portion of the semiconductor wafer.
2. The method of claim 1 , wherein the forming comprises forming the trap rich layer by one or more of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief, and mechanical texturing.
3. The method of claim 1 , further comprising:
before the bonding, forming one or more material layers at the top portion of the handle wafer above the trap rich layer.
4. The method of claim 3 , wherein the one or more material layers are one or more of an isolation layer and a bonding layer.
5. The method of claim 1 , wherein the bonding comprises bonding the top surface of the handle wafer to the top surface of the semiconductor wafer with the structure in the top portion of the handle wafer aligned with the active device.
6. A method comprising:
fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate, wherein the device layer comprises active devices;
etching a top portion of a handle wafer to form columns in the top portion of the handle wafer;
forming a trap rich layer conforming to the columns in the top portion of the handle wafer;
bonding a top surface of the handle wafer to a top surface of the semiconductor wafer with the active devices aligned with the columns; and
removing a bottom substrate portion of the semiconductor wafer.
7. The method of claim 6 , the forming comprises creating the trap rich layer by one or more of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief, and mechanical texturing.
8. The method of claim 6 , further comprising: forming a fill material on the columns.
9. The method of claim 8 , wherein the fill material is one of aluminum oxide, silicon carbide, aluminum nitride, and silicon dioxide.
10. The method of claim 6 , further comprising:
before the bonding, forming one or more material layers on the top portion of the handle wafer over the trap rich layer.
11. The method of claim 10 , wherein the one or more material layers are one or more of an isolation layer and a bonding layer.
12. The method of claim 6 , wherein the active devices comprise a radio frequency switch device.