Co-fabrication of non-planar semiconductor devices having different threshold voltages
Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.
1. A method, comprising:
providing a starting semiconductor structure, the starting semiconductor structure comprising a semiconductor substrate, a plurality of fins coupled to the substrate, at least two gate structures encompassing a portion of the fins, the at least two gate structures comprising at least two gate trenches, a conformal dielectric layer covering a bottom and walls of each of the at least two gate trenches, the at least two gate trenches being partially filled over the conformal dielectric layer with work function material, a portion of the work function material being recessed;
creating at least one conformal barrier layer in one or more and less than all of the at least two gate trenches;
filling the at least two gate trenches with conductive material; and
prior to the filling, modifying a work function of the work function material, resulting in different work functions for the at least two gate trenches with and without the conformal barrier layer.
2. The method of claim 1 , wherein the work function material of the starting structure comprises a n-type work function material.
3. The method of claim 1 , wherein the conformal dielectric layer of the starting semiconductor structure comprises a high-k dielectric.
4. The method of claim 3 , wherein the high-k dielectric comprises hafnium dioxide.
5. The method of claim 1 , wherein creating the at least one conformal barrier layer comprises:
creating a first conformal barrier layer over the starting semiconductor structure;
recessing a portion of the first conformal barrier layer above the recessed portion of the work function material; and
selectively removing the first conformal barrier layer from the at least one and less than all of the at least two gate structures.
6. The method of claim 5 , further comprising creating a second conformal barrier layer over a remainder of the first conformal barrier layer.
7. The method of claim 1 , wherein gate trenches with the at least one conformal barrier layer have a lower work function than gate trenches without the at least one conformal barrier layer.