IP Library Granted Patent US 9,576,101
Granted Patent B2
US 9,576,101 · App. 14/635,827 · Granted Feb 21, 2017

Configurable cell design using capacitive coupling for enhanced timing closure

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Quick Facts
Patent No.
US 9,576,101
App. No.
14/635,827
Granted
Feb 21, 2017
Kind
B2
Abstract

A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

Claims (17)

1. A method for designing an integrated circuit that satisfies time constraints using a processor-based design tool, the method comprising:

generating an initial integrated circuit design using a cell library of component cells and the design tool, wherein at least a first component cell in the initial integrated circuit design is part of a first subset of component cells having a same function and a same footprint;

performing a timing analysis on the initial integrated circuit design;

determining that the initial integrated circuit design does not satisfy the time constraints;

generating a modified integrated circuit design using the design tool by replacing the first component cell with a replacement component cell that (i) is part of the first subset of component cells and (ii) has a timing characteristic such that the modified integrated circuit design satisfies the time constraints, wherein the timing characteristics of the first component cell and the replacement component cell differ based on different capacitive coupling;

performing the timing analysis on the modified integrated circuit design;

determining whether the modified integrated circuit design satisfies the time constraints for the integrated circuit; and

fabricating an integrated circuit using the modified integrated circuit design,

wherein one of the first and replacement component cells is a faster component cell and the other is a slower component cell, and the slower component cell has stronger capacitive coupling than the faster component cell.

2. The method of claim 1 , wherein the stronger capacitive coupling results from out of phase signals travelling on a pair of traces in the slower component cell being closer together and longer than a corresponding pair of traces in the faster component cell.

3. The method of claim 2 , wherein all or a portion of the pair of traces in the slower component cell have a spacing that is less than a minimum spacing for conductors carrying clock signals throughout the integrated circuit for a technology node at which the integrated circuit is designed.

4. The method of claim 2 , wherein all or a portion of the pair of traces in the slower component cell have a spacing that is the spacing for conductors carrying non-clock signals for a technology node at which the integrated circuit is designed.

5. The method of claim 1 , wherein the stronger capacitive coupling results from a pair of traces in the slower component cell being longer than a corresponding pair of traces in the faster component cell.

6. The method of claim 5 , wherein the pair of traces in the slower component cell are nested boustrophedonic traces.

7. The method of claim 1 , wherein the first subset of component cells comprises a configurable component cell having a configurable layout that can be configured to provide different instantiations having different timing characteristics.

8. The method of claim 7 , wherein the configurable component cell is configured using jumpers to bridge discontinuous segments of traces.

9. The method of claim 8 , wherein at least one jumper is fabricated in a different metal layer than other traces of the configurable component cell.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0341 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0359 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0974 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0080 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0112 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0095 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: BHARGAVA, VIJAY; KUMAR, NAVEEN; KHORWAL, KUSHAGRA
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 035069/0539 →