Oscillation circuit and phase synchronization circuit
An oscillation circuit includes a ring oscillator and a current generating circuit. The ring oscillator includes a control terminal. The current generating circuit generates a current according to a voltage of the control terminal in the ring oscillator, and supplies the current to the control terminal. The ring oscillator includes a plurality of delay stages connected to each other in a ring shape. Each of the delay stages includes an inverter and a capacitance element. The inverter includes a power source side node, an input node, and an output node. The power source side node is connected to the control terminal. The capacitance element is connected as a load for the inverter. The capacitance value of the capacitance element is larger than a parasitic capacitance at the output node.
1. An oscillation circuit comprising:
a ring oscillator having a control terminal, an oscillation frequency of the ring oscillator being controllable by a drive current supplied to the control terminal; and
a current generating circuit configured to adjust the drive current to a level corresponding to a voltage of the control terminal and supply the drive current to the control terminal,
wherein the ring oscillator includes at least three delay elements connected in a ring shape,
wherein each delay element includes:
an inverter having a power source side node connected to the control terminal, an input node, and an output node; and
a capacitance element connected to the output node of the inverter and having a capacitance larger than a parasitic capacitance of the inverter at the output node,
wherein the input node of the inverter in each delay element is connected to the output node of the inverter in a different delay element,
wherein the current generating circuit includes a current setting resistor and the drive current is controlled to be proportional to a voltage across the current setting resistor,
wherein the current generating circuit further includes:
a compensation current generating section configured to generate a compensation current that is equivalent to a leakage current which does not contribute to oscillation in the ring oscillator; and
a current generating section configured to generate the drive current by adding the compensating current to a current proportional to the voltage across the current setting resistor,
wherein each inverter includes a first PMOS transistor and a first NMOS transistor, and
wherein the compensation current generating section includes:
a second PMOS transistor that corresponds in operational characteristics to the first PMOS transistor;
a second NMOS transistor that corresponds in operational characteristics to the first NMOS transistor;
a third PMOS transistor that corresponds in operational characteristics to the first PMOS transistor; and
a third NMOS transistor that corresponds in operational characteristics to the first NMOS transistor.
2. The oscillation circuit according to claim 1 , wherein the capacitance element in each delay element is connected between the respective output node of the delay element and a reference potential.
3. The oscillation circuit according to claim 1 , wherein the capacitance element of each delay element is connected between the respective power source side node and the output node of each delay element.
4. The oscillation circuit according to claim 1 , wherein
the second PMOS transistor includes a gate which is connected to the reference potential,
the second NMOS transistor includes a gate which is connected to the reference potential,
the third PMOS transistor includes a gate which is connected to a source of the third PMOS transistor, and
the third NMOS transistor includes a gate which is connected to the source of the third PMOS transistor.
5. The oscillation circuit according to claim 1 in a phase synchronization circuit, the phase synchronization circuit comprising:
a quantization section configured to generate phase information according to a phase of a periodical pulse which is output from the oscillation circuit;
a phase comparison section configured to acquire phase error information according to reference phase information and the phase information of the periodical pulse; and
a control section configured to control the oscillating frequency of the oscillation circuit according to the phase error information.
6. An oscillation circuit comprising:
a ring oscillator having a control terminal, an oscillation frequency of the ring oscillator being controllable by a drive current supplied to the control terminal; and
a current generating circuit configured to adjust the drive current to a level corresponding to a voltage of the control terminal and supply the drive current to the control terminal,
wherein the ring oscillator includes at least three delay elements connected in a ring shape,
wherein each delay element includes:
an inverter having a power source side node connected to the control terminal, an input node, and an output node; and
a capacitance element connected to the output node of the inverter and having a capacitance larger than a parasitic capacitance of the inverter at the output node,
wherein the input node of the inverter in each delay element is connected to the output node of the inverter in a different delay element,
wherein the current generating circuit includes a current setting resistor and the drive current is controlled to be proportional to a voltage across the current setting resistor, and
wherein the current generating circuit further includes:
a reference voltage generating section configured to generate a reference voltage which is equivalent to the voltage of the control terminal when the ring oscillator is operated; and
a current generating section configured to generate a current according to the reference voltage.
7. The oscillation circuit according to claim 6 ,
wherein each inverter includes a first PMOS transistor and a first NMOS transistor; and
wherein the reference voltage generating section includes:
a second PMOS transistor that corresponds in operational characteristics to the first PMOS transistor; and
a second NMOS transistor that corresponds in operational characteristics to the first NMOS transistor.
8. An oscillation circuit comprising:
a ring oscillator having a control terminal through which a drive current for the ring oscillator is supplied, an output terminal through which a signal oscillating at a frequency is supplied, the frequency being controllable by varying the drive current, and an odd number of adjacent delay stages having input and output nodes coupled together to form a ring; and
a current generating circuit that includes:
a differential amplifier having a first input terminal connected to a first node, a second input terminal connected to a second node, and an output node connected to a third node,
a first current source transistor connected between a first voltage and the first node,
a second current source transistor connected between the first voltage and the second node,
gates of the first and second current source transistors being connected to the third node,
a current setting resistor connected between the first node and ground voltage,
a second voltage at the second node corresponding to a ring oscillator voltage at the control terminal generated by operation of the ring oscillator, wherein
the drive current is controlled to correspond to current flowing through the first node, and
the current generating circuit further includes:
a voltage reference circuit connected to the second node and configured to supply an average reference voltage to the current setting resistor to control current in the current setting resistor; and
a current mirror configured to supply the drive current to the control terminal proportional to the current in the current setting resistor.
9. The oscillation circuit according to claim 8 ,
wherein each delay stage includes an inverter circuit and a capacitive load; and
wherein each inverter circuit includes:
a power source side node connected to the control terminal;
a connection to a reference potential;
an output node to which the capacitive load is attached; and
an input node connected to the output node of an adjacent delay stage.
10. The oscillation circuit according to claim 9 , wherein
the capacitive load has a value that is greater than a parasitic capacitance at the output node of the respective delay stage.
11. The oscillation circuit according to claim 10 , wherein the value of the capacitive load is such that an average current that flows through the power source side node is substantially equal to an average current which flows through the output node.
12. The oscillation circuit according to claim 8 , wherein the current generating circuit further includes:
a drive circuit under control of a digital control signal to supply a current proportional to current in the current mirror, the proportion being set by the digital control signal.
13. The oscillation circuit according to claim 12 , wherein the digital control signal is derived from an output of a digital filter configured to filter a difference between a phase quantized version of the signal output from the ring oscillator and a phase reference signal.