Temporary pipeline marking for processor error workarounds
Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
1. A method for temporary pipeline marking for processor error workarounds, the method comprising:
monitoring a pipeline of a processor for an event that is predetermined to: cause a stuck state that results in an errant instruction execution result due to the stuck state or a repeated resource contention causing a performance degradation, wherein the repeated resource contention is with respect to a shared resource;
marking the pipeline for a workaround action based on detecting the event;
triggering a clearing action based on the marking of the pipeline, wherein the triggering the clearing action comprises confirming that the event has occurred for a predetermined number of times; and
clearing the marking of the pipeline based on the triggering of the clearing action.
2. The method of claim 1 , wherein the clearing action comprises a complete purging of the pipeline.
3. The method of claim 2 , wherein the complete purging of the pipeline staggers timing of attempted accesses to the shared resource.
4. The method of claim 1 , wherein the pipeline is a load store unit pipeline and the event is associated with a memory address.
5. The method of claim 4 , wherein state information indicates a current state as a plurality of issued load store operations move through a plurality of stages of the load store unit pipeline.
6. A computer system for temporary pipeline marking for processor error workarounds, the computer system comprising:
a processor configured to perform a method comprising:
monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing a performance degradation, wherein the repeated resource contention is with respect to a shared resource;
marking the pipeline for a workaround action based on detecting the event;
triggering a clearing action based on the marking of the pipeline, wherein the triggering the clearing action comprises confirming that the event has occurred for a predetermined number of times; and
clearing the marking of the pipeline based on the triggering of the clearing action.
7. The computer system of claim 6 , wherein the clearing action comprises a complete purging of the pipeline.
8. The computer system of claim 7 , wherein the complete purging of the pipeline staggers timing of attempted accesses to the shared resource.
9. The computer system of claim 6 , wherein the pipeline is a load store unit pipeline and the event is associated with a memory address.
10. The computer system of claim 9 , wherein state information indicates a current state as a plurality of issued load store operations move through a plurality of stages of the load store unit pipeline.
11. A computer program product for temporary pipeline marking for processor error workarounds, the computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising:
computer readable program code configured for:
monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing a performance degradation, wherein the repeated resource contention is with respect to a shared resource;
marking the pipeline for a workaround action based on detecting the event;
triggering a clearing action based on the marking of the pipeline, wherein the triggering the clearing action comprises confirming that the event has occurred for a predetermined number of times; and
clearing the marking of the pipeline based on the triggering of the clearing action.
12. The computer program product of claim 11 , wherein the clearing action comprises a complete purging of the pipeline.
13. The computer program product of claim 12 , wherein the complete purging of the pipeline staggers timing of attempted accesses to the shared resource.
14. The computer program product of claim 11 , wherein the pipeline is a load store unit pipeline and the event is associated with a memory address.
15. The computer program product of claim 14 , wherein state information indicates a current state as a plurality of issued load store operations move through a plurality of stages of the load store unit pipeline.