IP Library Granted Patent US 10,153,174
Granted Patent B2
US 10,153,174 · App. 14/641,928 · Granted Dec 11, 2018

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 10,153,174
App. No.
14/641,928
Granted
Dec 11, 2018
Kind
B2
Abstract

A method of manufacturing a semiconductor device according to an embodiment includes forming a first interlayer film on a first layer, the first interlayer film containing a first molecule and a second molecule, and the first molecule and the second molecule being chemically bonded with each other. The method of manufacturing a semiconductor device includes phase-separating the first interlayer film. The method of manufacturing a semiconductor device includes forming a second layer on the phase-separated first interlayer film. The first molecule has a first affinity with the first layer and a second affinity with the second layer, the first affinity being larger than the second affinity. The second molecule has a third affinity with the second layer and a fourth affinity with the first layer, the third affinity being larger than the fourth affinity.

Claims (19)

1. A method of manufacturing a semiconductor device, comprising:

forming a first interlayer film on a first layer as an adhesive film, the first interlayer film containing a first molecule and a second molecule, and the first molecule and the second molecule being chemically bonded with each other;

phase-separating the first interlayer film, in which the first molecule and the second molecule are aligned with each other;

forming a second layer on the phase-separated first interlayer film;

contacting a patterned surface of a mold to transfer the pattern of the mold onto an upper surface of the second layer;

peeling the patterned surface of the mold off the upper surface of the second layer having the pattern transferred thereon; and

etching the first layer by only using the second layer as a mask,

wherein the first molecule has a first affinity with the first layer and a second affinity with the second layer and is chemically bonded with an upper surface of the first layer, the first affinity being larger than the second affinity, and

the second molecule has a third affinity with the second layer and a fourth affinity with the first layer and is chemically bonded with a lower surface of the second layer, the third affinity being larger than the fourth affinity.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the second layer is formed on the phase-separated first interlayer film after phase-separating the first interlayer film by heating the first interlayer film.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein the first interlayer film is phase-separated in a lamellar structure or a cylindrical structure by heating the first interlayer film.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein the first molecule is positioned on the side of the first layer and the second molecule is positioned on the side of the second layer.

5. The method of manufacturing a semiconductor device according to claim 3 , wherein the contacting of the patterned surface includes:

bringing the patterned surface of the mold, on which the pattern is formed, into contact with the upper surface of the second layer to transfer the pattern of the mold onto the upper surface of the second layer; and

curing the second layer.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein the first interlayer film is a self-assembly material in which molecules are aligned with each other when a phase separation occurs.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein the first interlayer film is made of a diblock copolymer.

8. The method of manufacturing a semiconductor device according to claim 7 , wherein the diblock copolymer is polystyrene-polymethylmethacrylate, the first molecule is polystyrene, and the second molecule is polymethylmethacrylate.

9. The method of manufacturing a semiconductor device according to claim 3 , wherein the second layer is a resist layer.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 043027 FRAME 0072. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043027/0072 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2015
From: OJIMA, TOMOKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035136/0391 →