Semiconductor device having vertical channel and air gap, and method of manufacturing thereof
A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.
1. A semiconductor device, comprising:
a plurality of word lines formed on a substrate;
a plurality of air gaps of which each air gap is interposed between two adjacent word lines;
a channel structure penetrating through the plurality of word lines and the plurality of air gaps; and
a plurality of memory cells of which each memory cell is interposed between each word line and the channel structure,
wherein each memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern,
wherein the blocking pattern of each memory cell conformally covers a top surface, a bottom surface, and a first side surface of each word line,
wherein the blocking pattern of each memory cell is vertically adjacent to another blocking pattern of a memory cell adjacent to and spaced apart from each memory cell,
wherein the first side surface is adjacent to the channel structure, and
wherein the charge trap pattern is interposed only between the first side surface and the channel structure.
2. The semiconductor device of claim 1 ,
wherein two adjacent charge trap patterns of two adjacent memory cells are spaced apart from each other in a direction perpendicular to a surface of the substrate.
3. The semiconductor device of claim 2 ,
wherein each air gap is further interposed between the two adjacent charge trap patterns.
4. The semiconductor device of claim 3 ,
wherein each air gap includes a first region having a first height and a second region having a second height,
wherein the first height is measured between a blocking pattern covering a bottom surface of one of two adjacent word lines and a blocking pattern covering a top surface of the other of the two adjacent word lines,
wherein the second height is measured between the two adjacent charge trap patterns, wherein the first height is smaller than the second height.
5. The semiconductor device of claim 2 , further comprising a plurality of oxide layers of which each oxide layer is interposed between the two adjacent charge trap patterns which are vertically spaced apart from each other.
6. The semiconductor device of claim 5 ,
wherein the two adjacent charge trap patterns and each oxide layer are vertically aligned.
7. The semiconductor device of claim 5 ,
wherein each air gap is enclosed by each oxide layer.
8. The semiconductor device of claim 1 ,
wherein a vertical length of the charge trap pattern is greater than a vertical length of the first side surface.
9. The semiconductor device of claim 1 ,
wherein a vertical length of the charge trap pattern is smaller than a vertical length of the blocking pattern, on the first side surface.
10. The semiconductor device of claim 1 ,
wherein the tunneling insulating pattern is interposed between the charge trap pattern and the channel structures.
11. The semiconductor device of claim 10 , further comprising an isolation pattern penetrating through the plurality of word lines and the plurality of air gaps.
12. The semiconductor device of claim 11 ,
wherein the isolation pattern is extended to enclose each air gap, wherein the isolation pattern is disposed on the blocking pattern, the charge trap pattern, and the tunneling insulating pattern.
13. The semiconductor device of claim 11 , further comprising a capping pattern formed between the isolation pattern and the word lines.
14. A semiconductor device comprising:
a stacked structure disposed on a substrate, wherein the stacked structure includes a first word line, an air gap and a second word line vertically stacked on each other, and wherein the air gap is interposed between the first word line and the second word line;
a channel structure adjacent to a first side of the stacked structure;
an isolation pattern adjacent to a second side of the stacked structure, wherein the second side is opposite to the first side;
a contiguous tunneling insulating pattern interposed between the stacked structure and the channel structure; a first charge trap pattern interposed between the first word line and the channel structure;
a second charge trap pattern interposed between the first charge trap pattern and the channel structure;
a first blocking pattern having a first portion interposed between the first word line and the first charge trap pattern and a second portion interposed between the first word line and the air gap; and
a second blocking pattern interposed between the second word line and the contiguous tunneling insulating pattern.
15. The semiconductor device of claim 14 ,
wherein the air gap is further interposed between the first charge trap pattern and the second charge trap pattern.
16. The semiconductor device of claim 14 ,
wherein the isolation pattern includes a first extended portion, a second extended portion and a third extended portion, wherein the first extended portion is interposed between the air gap and the first portion of the first blocking pattern, wherein the second extended portion is interposed between the air gap and the first portion of the second blocking pattern, and wherein the third extended portion is interposed between the air gap and the contiguous tunneling insulating pattern.
17. A semiconductor device, comprising:
word lines and air gaps, which are alternately and repeatedly formed on a substrate;
channel structures configured to vertically pass through the word lines and the air gaps and connected to the substrate;
blocking patterns formed between the word lines and the air gaps and on sides of the word lines facing the channel structures;
charge trap patterns formed on the blocking patterns formed on the sides of the word lines;
tunneling insulating patterns formed between the charge trap patterns and the channel structures; and
oxide layers, wherein each of the oxide layers is disposed between two adjacent word lines and defines each of the air gaps,
wherein the oxide layers are vertically spaced apart from each other, and
wherein the charge trap patterns are vertically spaced apart from each other.
18. The semiconductor device according to claim 17 ,
wherein the charge trap patterns and the oxide layers are vertically aligned.
19. The semiconductor device according to claim 17 ,
wherein a vertical length of the charge trap pattern is greater than a vertical length of a side of the word line, and smaller than vertical lengths of the blocking patterns.
20. The semiconductor device according to claim 17 ,
wherein each of the oxide layers is in contact with two adjacent charge trap patterns.