Integrated circuit packaging system with insulated trace and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a substrate;
forming a plain trace on the substrate;
forming an insulated trace on the substrate;
depositing an insulation layer on a portion of a trace top surface of the insulated trace,
the insulation layer spaced away from the plain trace; and
mounting a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached directly on the trace top surface of the insulated trace, and the plain bump is mounted adjacent to the insulation layer, and sections of the insulated trace adjacent to the plain bump are fully insulated by the insulation layer.
2. The method as claimed in claim 1 further comprising:
disposing a protection layer on the substrate, and the protection layer at least partially exposes the plain trace and the insulated trace.
3. The method as claimed in claim 1 wherein:
forming the plain trace includes forming the plain trace on a substrate top surface, a trace top surface and vertical surfaces of the plain trace are exposed above the substrate top surface; and
forming the insulated trace includes forming the insulated trace on the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are exposed above the substrate top surface.
4. The method as claims in claim 1 wherein:
forming the plain trace includes forming the plain trace under a substrate top surface,
a trace top surface and vertical surfaces of the plain trace are embedded under the substrate top surface; and
forming the insulated trace includes forming the insulated trace under the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are embedded under the substrate top surface.
5. The method as claimed in claim 1 wherein:
depositing the insulation layer includes depositing the insulation layer using direct patterning techniques.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a substrate;
forming a plain trace on the substrate, the plain trace has a bump pad thereon; forming an insulated trace on the substrate, the insulated trace has the bump pad thereon;
depositing an insulation layer on a portion of a trace top surface of the insulated trace, the insulation layer spaced away from the plain trace and the insulation layer adjacent to the bump pad of the plain trace; and mounting a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached directly on the trace top surface of the insulated trace, the plain bump is mounted adjacent to the insulation layer, and sections of the insulated trace adjacent to the plain bump are fully insulation by the insulation layer.
7. The method as claimed in claim 6 further comprising: forming a protection layer on the substrate, the protection layer has a lower area and
upper areas at least partially exposing the plain trace and the insulated trace.
8. The method as claimed in claim 6 wherein: forming the plain trace includes forming the plain trace on a substrate top surface, a
trace top surface and vertical surfaces of the plain trace are exposed above the substrate top surface, the plain trace is adjacent to the insulated trace; and forming the insulated trace includes forming the insulated trace on the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are exposed above the substrate top surface, the insulated trace has a length different than the plain trace;
forming the insulated trace includes forming an insulated trace on the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are exposed above the substrate top surface.
9. The method as claimed in claim 6 wherein: forming the plain trace includes forming the plain trace under a substrate top surface,
a trace top surface and vertical surfaces of the plain trace are embedded under the substrate top surface, the plain trace is adjacent to the insulated trace; and forming the insulated trace includes forming the insulated trace under the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are embedded under the substrate top surface, the insulated trace has a length different than the plain trace.
10. The method as claimed in claim 6 wherein:
depositing the insulation layer includes depositing the insulation layer using direct patterning techniques with dielectric ink followed by a dielectric ink curing process.
11. An integrated circuit packaging system comprising:
a substrate;
a plain trace on the substrate, the plain trace has a bump pad on the plain trace;
an insulated trace on the substrate, the insulated trace has the bump pad on the insulated trace;
a protection layer on the substrate, the protection layer has a lower area and upper areas at least partially exposing the plain trace and the insulated trace;
an insulation layer on a portion of a trace top surface of the insulated trace, the insulation layer spaced away from the plain trace; and
a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the bump pad of the plain trace and an inner bump attached directly on the trace top surface of the insulated trace, and the plain bump is mounted adjacent to the insulation layer.
12. The system as claimed in claim 11 wherein:
the plain trace includes the plain trace on a substrate top surface, a trace top surface and vertical surfaces of the plain trace are exposed above the substrate top surface; and
the insulated trace includes the insulated trace on the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are exposed above the substrate top surface.
13. The system as claimed in claim 11 wherein:
the plain trace includes the plain trace under a substrate top surface, a trace top surface and vertical surfaces of the plain trace are embedded under the substrate top surface; and
the insulated trace includes the insulated trace under the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are embedded under the substrate top surface.
14. The system as claimed in claim 11 wherein:
the plain bump and the inner bump are attached on interconnectors of an active side of the semiconductor device.
15. The system as claimed in claim 11 wherein:
the plain trace includes the plain trace on a substrate top surface, a trace top surface and vertical surfaces of the plain trace are exposed above the substrate top surface, the plain trace is adjacent to the insulated trace, the plain bump is attached to the top surface and the vertical surfaces of the plain trace; and
the insulated trace includes the insulated trace on the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are exposed above the substrate top surface, the insulated trace has a length different than the plain trace, the inner bump is attached to the top surface and the vertical surfaces of the insulated trace.
16. The system as claimed in claim 11 wherein:
the plain trace includes the plain trace under a substrate top surface, a trace top surface and vertical surfaces of the plain trace are embedded under the substrate top surface, the plain trace is adjacent to the insulated trace, the plain bump is attached to the top surface of the plain trace; and
the insulated trace includes the insulated trace under the substrate top surface, the trace top surface and vertical surfaces of the insulated trace are embedded under the substrate top surface, the insulated trace has a length different than the plain trace, the inner bump is attached to the top surface of the insulated trace.
17. The system as claimed in claim 11 wherein:
the plain bump and the inner bump are attached on interconnectors of an active side of the semiconductor device, and electrically connect the semiconductor device to the substrate.