Semiconductor device including subword driver circuit
The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK 1 or VKK 2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK 1 or VKK 2.
1. A semiconductor device comprising:
a plurality of subword lines;
a plurality of bit lines;
a plurality of memory cells, each arranged at intersection positions of the plurality of subword lines and the plurality of the bit lines;
a plurality of subword driver circuits, each coupled to associated one of the subword lines and configured to supply one of a first non selection potential, a second non selection potential lower than the first non selection potential and a third selection potential different from the first and second non selection potentials; and
a select circuit configured to supply at least one of the first and second non selection potentials to a second node,
wherein the select circuit comprises:
a first transistor coupled between a first potential line and the second node, the first potential line configured to supply the first non selection potential;
a second transistor coupled between a second potential line and the second node, the second potential line configured to supply the second non selection potential;
a third transistor coupled between a third potential line and the second node, the third potential line configured to supply a third non selection potential that is higher than the first non selection potential; and
a fourth transistor coupled between a fourth potential line and the second node, the fourth potential line configured to supply a fourth non selection potential that is lower than the second non selection potential.
2. The semiconductor device as claimed in claim 1 , wherein
each of the plurality of subword driver circuits includes a fifth transistor coupled between a first node supplying one of complementary drive signals and an associated one of the plurality of subword lines, a sixth transistor coupled between the associated one of the plurality of subword lines and the second node, each control terminal of the fifth and sixth transistors receiving an associated one of a plurality of main word signals, a seventh transistor coupled between the associated one of the plurality subword lines and the second node, and the seventh transistor including a control terminal receiving an other of the complementary drive signals.
3. The semiconductor device as claimed in claim 1 , wherein each of the first and second non selection potentials is a negative potential and the third selection potential is a positive potential.
4. The semiconductor device as claimed in claim 1 , wherein each of the plurality of memory cells includes:
a transistor including a control terminal coupled to an associated one of the plurality of subword lines, and
a storage element,
wherein the transistor and the storage element coupled in series to an associated one of the plurality of bit lines.
5. The semiconductor device as claimed in claim 1 ,
wherein the third non selection potential is a power supply potential, and
wherein the fourth non selection potential is a substrate potential.
6. The semiconductor device as claimed in claim 1 , wherein
the first transistor is configured to receive a first selection signal,
wherein the second transistor is configured to receive a second selection signal,
wherein the third transistor is configured to receive a third selection signal, and
wherein the fourth transistor is configured to receive a fourth selection signal.
7. A semiconductor device comprising:
a first subword line coupled to a memory cell;
a first subword driver circuit coupled to the first subword line, the first subword driver circuit configured to supply at least one of a first negative potential and a second negative potential different from the first negative potential to the first subword line; and
a select circuit configured to supply at least one of the first negative potential and the second negative potential to a second node coupled to the first subword driver circuit,
wherein the select circuit includes a first transistor coupled between a first potential line and the second node, the first potential line configured to supply the first negative potential,
wherein the select circuit further includes a capacitor having one end coupled to a drain node of the first transistor at the second node, with a first selection signal being supplied to another end, and
wherein the first subword driver circuit is configured to supply a potential on the second node to the first subword line.
8. The semiconductor device as claimed in claim 7 , wherein the first subword driver circuit is configured to supply one of the first negative potential, the second negative potential, a third positive potential different from the first and second negative potentials.
9. The semiconductor device as claimed in claim 7 , wherein the memory cell includes:
a transistor including a control terminal coupled to the subword line, and
a storage element,
wherein the transistor and the storage element coupled in series to a bit line.
10. The semiconductor device as claimed in claim 7 , wherein the first subword driver circuit is configured to supply at least one of the responsive to a main word signal and complementary drive signals.
11. The semiconductor device as claimed in claim 7 , wherein the capacitor is configured to change a potential level of the second node from the first negative potential to the second negative potential responsive to the first selection signal when the first transistor is turned off.
12. A semiconductor device comprising:
a first subword line;
a first memory cell coupled to the first subword line;
a first subword driver circuit coupled to the first subword line to drive the first subword line; and
a selection circuit coupled to the first subword driver circuit and configured to supply at least one of a first potential, and a second potential lower than the first potential,
wherein the selection circuit includes:
a first transistor coupled between a first potential line and a second node, the first potential line configured to supply the first potential;
a second transistor coupled between a second potential line and the second node, the second potential line configured to supply the second potential;
a third transistor coupled between a third potential line and the second node, the third potential line configured to supply a third potential higher than the first potential; and
a fourth transistor coupled between a fourth potential line and the second node, the fourth potential line configured to supply a fourth potential lower than the second potential.
13. The semiconductor device as claimed in claim 12 , wherein the first subword driver includes a fifth transistor coupled between a first node and the first subword line, the first node configured to supply one of complementary drive signals, a sixth transistor coupled between the first subword line and the second node, control terminals of the fifth and sixth transistors an associated one of a plurality of main word signals, a seventh transistor coupled between the first subword line and the second node, and the seventh transistor including a control terminal receiving an other of the complementary drive signals.
14. The semiconductor device as claimed in claim 12 , wherein each of the first and second potentials is a negative potential.
15. The semiconductor device as claimed in claim 12 ,
wherein the third potential is a power supply potential, and
wherein the fourth potential is a substrate potential.