IP Library Granted Patent US 9,201,731
Granted Patent B2
US 9,201,731 · App. 14/642,526 · Granted Dec 1, 2015

Error correction for storage devices

Inventors: Gregory Burd (San Jose, CA); Nedeljko Varnica (San Jose, CA); Heng Tang (San Jose, CA)
Assignee: Marvell World Trade Ltd.
G06F11/1076G11B20/1833G11B20/1217
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Quick Facts
Patent No.
US 9,201,731
App. No.
14/642,526
Granted
Dec 1, 2015
Kind
B2
Abstract

Systems and techniques relating to fault tolerant data storage in storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR) and/or storage devices that employ solid state memory, include a method, in some implementations, including: receiving, at a storage controller, a data request for a storage device; reading, in response to the data request, data from discrete units of storage in the storage device, the data comprising stored data read from two or more of the discrete units of storage and parity data read from at least one of the discrete units of storage; detecting an error in the stored data from the reading; and recovering stored data for at least one of the discrete units of storage using the parity data and the stored data read from one or more remaining ones of the two or more of the discrete units of storage.

Claims (28)

1. A method comprising:

receiving, at a storage controller, a data request for a storage device;

reading, in response to the data request, data from discrete units of storage in the storage device, the data comprising stored data read from two or more of the discrete units of storage and parity data read from at least one of the discrete units of storage;

detecting an error in the stored data from the reading; and

recovering stored data for at least one of the discrete units of storage using the parity data and the stored data read from one or more remaining ones of the two or more of the discrete units of storage.

2. The method of claim 1 , comprising using an error correcting code for data read from the discrete units of storage, and detecting the error comprises the error correcting code failing for the stored data for the at least one of the discrete units of storage.

3. The method of claim 1 , wherein the discrete units of storage are a first type of storage unit located in a second type of storage unit in the storage device, the discrete units of storage of the first type are each of equal size, and the second type of storage unit is larger than the first type of storage unit.

4. The method of claim 3 , wherein the storage device comprises solid state memory circuitry, and the method comprises identifying the discrete units of storage based on the data request.

5. The method of claim 4 , wherein the second type of storage unit is a solid state memory device, and the first type of storage unit is an integrated circuit die within a solid state memory device.

6. The method of claim 4 , wherein the second type of storage unit is an integrated circuit die of a solid state memory device, and the first type of storage unit is an individually addressable memory block within an integrated circuit die of a solid state memory device.

7. The method of claim 4 , wherein the second type of storage unit is an individually addressable memory block within an integrated circuit die of a solid state memory device, and the first type of storage unit is a page within an individually addressable memory block within an integrated circuit die of a solid state memory device.

8. The method of claim 3 , wherein the storage device comprises a shingled magnetic recording (SMR) medium.

9. The method of claim 8 , wherein the second type of storage unit is a SMR track within the SMR medium, and the first type of storage unit is a sector within the SMR track within the SMR medium.

10. The method of claim 9 , wherein the discrete units of storage of the SMR track compose a first section of the SMR track, the reading comprises reading the SMR track in its entirety, including additional stored data and additional parity data from one or more additional sections of the SMR track, and the method comprises recovering stored data for one or more of the one or more additional sections of the SMR track when an error correcting code fails for at least one discrete portion of the one or more additional sections of the SMR track.

11. The method of claim 9 , wherein the SMR track is a first SMR track of the SMR medium, and the method comprises initiating reading of a second SMR track, which is at a different location in the SMR medium than the first SMR track, before completing the recovering for the first SMR track.

12. A storage system comprising:

discrete units of storage in a storage device; and

a controller configured to receive a data request for the storage device, read data from the discrete units of storage in the storage device responsive to the data request, including stored data read from two or more of the discrete units of storage and parity data read from at least one of the discrete units of storage, and recover stored data for at least one of the discrete units of storage using the parity data and the stored data read from one or more remaining ones of the two or more of the discrete units of storage.

13. The storage system of claim 12 , wherein the controller is configured to use an error correcting code for data read from the discrete units of storage, and recover the stored data for the at least one of the discrete units of storage when the error correcting code fails for the stored data for the at least one of the discrete units of storage.

14. The storage system of claim 12 , wherein the discrete units of storage are a first type of storage unit located in a second type of storage unit in the storage device, the discrete units of storage of the first type are each of equal size, and the second type of storage unit is larger than the first type of storage unit.

15. The storage system of claim 14 , wherein the storage device comprises solid state memory circuitry, and the controller is configured to identify the discrete units of storage based on the data request.

16. The storage system of claim 15 , wherein the second type of storage unit is a solid state memory device, and the first type of storage unit is an integrated circuit die within a solid state memory device.

17. The storage system of claim 15 , wherein the second type of storage unit is an integrated circuit die of a solid state memory device, and the first type of storage unit is an individually addressable memory block within an integrated circuit die of a solid state memory device.

18. The storage system of claim 15 , wherein the second type of storage unit is an individually addressable memory block within an integrated circuit die of a solid state memory device, and the first type of storage unit is a page within an individually addressable memory block within an integrated circuit die of a solid state memory device.

19. The storage system of claim 14 , wherein the storage device comprises a shingled magnetic recording (SMR) medium.

20. The storage system of claim 19 , wherein the second type of storage unit is a SMR track within the SMR medium, and the first type of storage unit is a sector within the SMR track within the SMR medium.

21. The storage system of claim 20 , wherein the discrete units of storage of the SMR track compose a first section of the SMR track, the reading comprises reading the SMR track in its entirety, including additional stored data and additional parity data from one or more additional sections of the SMR track, and the method comprises recovering stored data for one or more of the one or more additional sections of the SMR track when an error correcting code fails for at least one discrete portion of the one or more additional sections of the SMR track.

22. The storage system of claim 20 , wherein the SMR track is a first SMR track of the SMR medium, and the method comprises initiating reading of a second SMR track, which is at a different location in the SMR medium than the first SMR track, before completing the recovering for the first SMR track.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2015
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 036087/0336 →
Continuity (8)
Continuation 14466881 · Aug 22, 2014
Continuation In Part 14260237 · Apr 23, 2014
Continuation 13844302 · Mar 15, 2013
Continuation 12881881 · Sep 14, 2010
Provisional Application 61254577 · Oct 23, 2009
Provisional Application 61876360 · Sep 11, 2013
Provisional Application 61242662 · Sep 15, 2009
Related Publication 20150178161A1 · Jun 25, 2015