Low-test memory stack for non-volatile storage
The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.
1. A method for packaging non-volatile memory, comprising:
selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and
packaging the selected plurality of non-volatile memory die.
2. The method of claim 1 , wherein the selecting includes:
in accordance with the statistical die performance information, selecting a number of die so as to over-provision the packaged non-volatile memory to guarantee, within a predefined statistical tolerance, at least a predefined amount of programmable/erasable memory in the packaged non-volatile memory.
3. The method of claim 1 , further including:
after said packaging, performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.
4. The method of claim 3 , wherein at least one test of the set of tests is performed by a host system under control of system application software.
5. The method of claim 1 , wherein the one or more tests that have been deferred until after packaging include at least one predefined die-level test.
6. The method of claim 1 , wherein the one or more tests that have been deferred until after packaging include at least one predefined sub-die-level test.
7. The method of claim 1 , further including:
deferring, at least until the selected plurality of non-volatile memory die are packaged, performance of at least one of the following tests: a wafer sort test, a known good die test, and a burn-in test.
8. The method of claim 1 , further including:
forgoing performance of at least one of the following tests: a wafer sort test, a memory component test, a known good die test, and a burn-in test.
9. The method of claim 1 , further including:
after packaging the plurality of non-volatile memory die, determining an amount of programmable/erasable memory in the packaged non-volatile memory.
10. The method of claim 1 , further including:
after packaging the plurality of non-volatile memory die, during initialization of the packaged non-volatile memory, performing an initialization procedure that includes:
determining a validity state of one or more units of memory of the plurality of non-volatile memory die, the validity state being one of a valid state or an invalid state; and
using physical-to-physical address remapping to redirect a read/write request addressed to a respective unit of memory having an invalid state to a unit of memory having a valid state.
11. The method of claim 10 , wherein determining the validity state of the one or more units of memory includes:
determining a validity metric of the one or more units of memory; and
comparing the validity metric to a predefined threshold to determine the validity state of the one or more units of memory.
12. The method of claim 11 , wherein the validity metric is a bit error rate (BER) of the one or more units of memory during initialization.
13. The method of claim 11 , further including:
writing to the plurality of non-volatile memory die in accordance with a wear leveling algorithm that accounts for the validity metric determined during initialization.
14. The method of claim 1 , wherein the set of non-volatile memory die comprises flash memory.
15. The method of claim 1 , wherein a median number of program/erase (P/E) cycles performed on units of memory of the plurality of non-volatile memory die prior to the packaging is less than fifty P/E cycles.
16. A storage system, comprising:
an interface for operatively coupling the storage system with a host system; and
a plurality of non-volatile memory die selected and packaged in accordance with the method of claim 1 .