IP Library Granted Patent US 10,008,390
Granted Patent B2
US 10,008,390 · App. 14/643,218 · Granted Jun 26, 2018

Manufacturing method of semiconductor device and semiconductor manufacturing apparatus

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Quick Facts
Patent No.
US 10,008,390
App. No.
14/643,218
Granted
Jun 26, 2018
Kind
B2
Abstract

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.

Claims (27)

1. A manufacturing method of a semiconductor device, the method comprising:

implanting ions of C or Si serving as impurities into an outer peripheral portion of the polishing target film to cause an impurity concentration of ions of C or Si to be larger than an impurity concentration of ions of F, B, P, or N in the outer peripheral portion, so as to modify a surface of the polishing target film;

thermally treating the polishing target film at a temperature equal to or higher than 900 degrees Celsius after the implantation of the ions of C or Si and before a polishing of the polishing target film;

polishing the modified surface of the polishing target film by a CMP method, and

implanting ions of F, B, P, or N serving as impurities into the central portion of the polishing target film to cause an impurity concentration of ions of F, B, P, or N to be larger than an impurity concentration of ions of C or Si in the central portion after the thermally treatment and before the polish.

2. The method of claim 1 , wherein the impurities are implanted a plurality of times at a plurality of acceleration energies different from each other.

3. The method of claim 1 , wherein the impurities are implanted to cause a concentration profile in a depth direction of the polishing target film to have a plurality of peaks.

4. The method of claim 1 , wherein the impurities are implanted at a concentration equal to or higher than 10 19 cm −3 .

5. The method of claim 1 , wherein a polishing agent in the CMP method is slurry containing CeO 2 or SiO 2 .

6. The method of claim 1 , wherein the outer peripheral portion of the polishing target film into which the ions are implanted is a first area, in which patterns are not formed, outside of a chip area in which patterns are formed.

7. The method of claim 6 , wherein a dopant to be implanted into the first area or a dose amount thereof is changed according to an occupancy rate of the first area or an occupancy rate of convex portions in the patterns.

8. The method of claim 1 , wherein

a width of the outer peripheral portion of the polishing target film is less than 1/10 of a diameter of the polishing target film.

9. A manufacturing method of a semiconductor device, the method comprising:

implanting ions of N serving as impurities into an outer peripheral portion of the polishing target film to cause an impurity concentration of ions of N to be larger than an impurity concentration of ions of F, B, or P in the outer peripheral portion, so as to modify a surface of the polishing target film;

thermally treating the polishing target film at a temperature equal to or higher than 900 degrees Celsius after the implantation of the ions of N and before a polishing of the polishing target film;

polishing the modified surface of the polishing target film by a CMP method; and

implanting ions of F, B or P serving as impurities into the central portion of the polishing target film to cause an impurity concentration of ions of F, B or P to be larger than an impurity concentration of ions of N in the central portion after the thermally treatment and before the polish.

10. The method of claim 9 , wherein

a width of the outer peripheral portion of the polishing target film is less than 1/10 of a diameter of the polishing target film.

11. A manufacturing method of a semiconductor device, the method comprising:

implanting ions of N into an outer peripheral portion of a polishing target film using one of the ion beam masks;

thermally treating the polishing target film at a temperature equal to or higher than 900 degrees after implanting the ions N into the outer peripheral portion;

implanting ions of F, B, P, or N into the central portion of the polishing target film using another one of the ion beam masks after the thermal treatment; and

polishing the surface of the polishing target film by a CMP method after the implantation of the ions of F, B, P, or N.

12. The method of claim 11 , wherein

a width of the outer peripheral portion of the polishing target film is less than 1/10 of a diameter of the polishing target film.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 043027 FRAME 0072. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043027/0072 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2015
From: MATSUI, YUKITERU; SUGURO, KYOICHI; GAWASE, AKIFUMI; KAWASAKI, TAKAHIKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035670/0888 →