IP Library Granted Patent US 9,793,102
Granted Patent B2
US 9,793,102 · App. 14/644,952 · Granted Oct 17, 2017

Semiconductor manufacturing apparatus and semiconductor manufacturing method

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Quick Facts
Patent No.
US 9,793,102
App. No.
14/644,952
Granted
Oct 17, 2017
Kind
B2
Abstract

In one embodiment, a semiconductor manufacturing apparatus includes a stage provided in a chamber, and a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage. The apparatus further includes a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of wafers on the stage by the conveying module according to the treatment periods.

Claims (42)

1. A semiconductor manufacturing apparatus comprising:

a stage provided in a chamber;

a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage;

a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of wafers on the stage by the conveying module according to the treatment periods.

2. The apparatus of claim 1 , wherein the division number K of the first to K-th treatment periods is equal to a number of the plurality of wafers.

3. The apparatus of claim 1 , wherein the division number K of the first to K-th treatment periods is less than a number of the plurality of wafers.

4. The apparatus of claim 1 , wherein the controller changes the positions of the wafers so that the positions of the wafers are switched with each other.

5. The apparatus of claim 1 , wherein

the plurality of wafers include first to N-th wafers where N is an integer of two or more, and

the controller accesses a process amount storage module configured to store first to N-th process amounts for the first to N-th wafers, and changes the positions of one or more of the first to N-th wafers so that process amounts of the first to N-th wafers in the first to K-th treatment periods respectively become the first to N-th process amounts.

6. The apparatus of claim 5 , wherein the controller accesses a wafer information storage module configured to store a number of the plurality of wafers, and determines the division number K of the first to K-th treatment periods based on the number of the plurality of wafers.

7. The apparatus of claim 5 , wherein the controller accesses a process characteristics storage module configured to store a process characteristic of the semiconductor manufacturing apparatus for processing the wafers, and determines the positions of the wafers based on the process characteristic.

8. The apparatus of claim 5 , wherein the process amounts are amounts related to formation of a film onto the wafers, removal of a film on the wafers, or impurity implantation to the wafers.

9. The apparatus of claim 1 , wherein the controller equally divides the treatment time into the first to K-th treatment periods.

10. The apparatus of claim 1 , wherein the controller unequally divides the treatment time into the first to K-th treatment periods.

11. A semiconductor manufacturing method comprising:

conveying a plurality of wafers into a chamber;

setting the plurality of wafers on a stage in the chamber; and

dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,

wherein the division number K of the first to K-th treatment periods is equal to a number of the plurality of wafers.

12. The method of claim 11 , wherein the positions of the wafers are changed so that the positions of the wafers are switched with each other.

13. The method of claim 11 , wherein the treatment time is equally divided into the first to K-th treatment periods.

14. A semiconductor manufacturing method comprising:

conveying a plurality of wafers into a chamber;

setting the plurality of wafers on a stage in the chamber; and

dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,

wherein the division number K of the first to K-th treatment periods is less than a number of the plurality of wafers.

15. A semiconductor manufacturing method comprising:

conveying a plurality of wafers into a chamber;

setting the plurality of wafers on a stage in the chamber; and

dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,

wherein:

the plurality of wafers include first to N-th wafers where N is an integer of two or more, and

the method further comprises accessing a process amount storage module configured to store first to N-th process amounts for the first to N-th wafers, and changing the positions of one or more of the first to N-th wafers so that process amounts of the first to N-th wafers in the first to K-th treatment periods respectively become the first to N-th process amounts.

16. The method of claim 15 , further comprising accessing a wafer information storage module configured to store a number of the plurality of wafers, and determining the division number K of the first to K-th treatment periods based on the number of the plurality of wafers.

17. The method of claim 15 , further accessing a process characteristics storage module configured to store a process characteristic of a semiconductor manufacturing apparatus for processing the wafers, and determining the positions of the wafers based on the process characteristic.

18. The method of claim 15 , wherein the process amounts are amounts related to formation of a film onto the wafers, removal of a film on the wafers, or impurity implantation to the wafers.

19. A semiconductor manufacturing method comprising:

conveying a plurality of wafers into a chamber;

setting the plurality of wafers on a stage in the chamber; and

dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,

wherein the treatment time is unequally divided into the first to K-th treatment periods.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 043027 FRAME 0072. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043027/0072 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2015
From: MIURA, KAZUYUKI; TAKAHASHI, KENSUKE
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035436/0314 →