Non-volatile semiconductor memory device and manufacturing method thereof

1. A non-volatile semiconductor memory device, comprising:

a memory cell array including NAND cell units arranged therein, the NAND cell unit being configured to extend in a first direction vertical to a surface of a semiconductor substrate, the NAND cell unit being formed by coupling a plurality of memory cells and selection transistors in series; and

a local source line formed on the semiconductor substrate, the local source line being electrically coupled to one end of the NAND cell unit, wherein

the memory cell array includes:

a laminated body where a plurality of conductive films are laminated sandwiching an interlayer insulating film, the conductive film being a control gate line of the memory cell or a selection gate line of the selection transistor;

a semiconductor layer that extends in the first direction; and

an electric charge accumulating layer sandwiched between the semiconductor layer and the conductive film,

the local source line includes a silicide layer, and

the electric charge accumulating layer is continuously formed from the memory cell array to cover a whole of a peripheral surface of the silicide layer.

2. The non-volatile semiconductor memory device according to claim 1 , further comprising

an element isolation insulating film that extends in the first direction to separate a plurality of the conductive films in a position between a plurality of the NAND cell units, and

one end of the element isolation insulating film reaches the silicide layer.

3. The non-volatile semiconductor memory device according to claim 2 , wherein

the element isolation insulating film includes:

a first element isolation insulating film that separates only the conductive films to be the selection gate lines of the selection transistors; and

a second element isolation insulating film that separates both the selection gate lines of the selection transistors and the control gate lines of the memory cells.

4. The non-volatile semiconductor memory device according to claim 3 , wherein

the first element isolation insulating film and the second element isolation insulating film are alternately disposed along a second direction intersecting with the first direction.

5. The non-volatile semiconductor memory device according to claim 1 , wherein

the local source line is coupled to one end of a source-side contact that extends in the first direction, and another end of the source-side contact is coupled to a global source line.

6. The non-volatile semiconductor memory device according to claim 5 , further comprising:

an isolation insulating film that extends in the first direction to separate a plurality of the conductive films in a position between a plurality of the NAND cell units, and

one end of the isolation insulating film reaches the silicide layer.

7. The non-volatile semiconductor memory device according to claim 6 , wherein

the isolation insulating film includes:

a first isolation insulating film that separates only the conductive films to be the selection gate lines of the selection transistors; and

a second isolation insulating film that separates both the selection gate lines of the selection transistors and the control gate lines of the memory cells.

8. The non-volatile semiconductor memory device according to claim 7 , wherein

the first isolation insulating film and the second isolation insulating film are alternately disposed along a second direction intersecting with the first direction.

9. The non-volatile semiconductor memory device according to claim 1 , wherein

the silicide layer has a hollow portion inside.

10. The non-volatile semiconductor memory device according to claim 1 , wherein

the local source line includes a diffusion layer between the electric charge accumulating layer and the silicide layer.