Memory controllers to form symbols based on bursts

1. A system comprising:

a memory comprising a plurality of pins; and

a memory controller to interface with the memory based on a codeword including a plurality of n-bit symbols, wherein an n-bit symbol of the codeword is formed from a burst of a plurality of bits over time output by a single pin of the plurality of pins of the memory,

the memory controller to correct an error of the memory using the n-bit symbol formed from the burst of the plurality of bits, wherein the memory controller stores an indication of a hard pin failure of a first pin of the memory based on a previously corrected pin failure, and tolerates a plurality of pin failures based on the stored indication, a check symbol, and erasure coding.

2. The system of claim 1 , wherein the memory includes a plurality of dynamic random-access memory (DRAM) chips, and a respective DRAM chip of the plurality of DRAM chips is associated with a number of symbols corresponding to a number of pins of the respective DRAM chip.

3. The system of claim 1 , wherein the memory comprises a 72-pin dual in-line memory module (DIMM), and the codeword includes 64 8-bit vertical data symbols and 8 8-bit vertical check symbols based on burst data transfers, each 8-bit vertical data symbol of the 64 8-bit vertical data symbols formed from a burst of 8 bits from a respective single pin of the DIMM, and each 8-bit vertical check symbol of the 8 8-bit vertical check symbols formed from a burst of 8 bits from a respective single pin of the DIMM.

4. The system of claim 3 , wherein the memory controller is to correct up to 4 symbol errors, based on an ECC code and the 8 8-bit vertical check symbols.

5. The system of claim 1 , wherein a pin of the plurality of pins of the memory is shared by a plurality of stacked memory dies.

6. The system of claim 1 , wherein the plurality of n-bit symbols of the codeword includes an n-bit check symbol for multiple n-bit data symbols.

7. The system of claim 1 , wherein the memory comprises a double data rate (DDRx) synchronous dynamic random-access memory (SDRAM), where x is an integer greater than one and corresponds to a burst data transfer rate of n bursts.

8. The system of claim 1 , wherein a first n-bit symbol of the plurality of n-bit symbols is formed from a burst of multiple bits output by a first pin of the memory, and a second n-bit symbol of the plurality of n-bit symbols is formed from a burst of multiple bits output by a second pin of the memory, wherein errors in other pins of the plurality of pins other than the first pin do not affect the first n-bit symbol.

9. The system of claim 1 , wherein the burst of the plurality of bits over time output by the single pin is part of a burst access of a double data rate (DDR) memory.

10. The system of claim 1 , wherein the n-bit symbol formed from the burst of the plurality of bits is a first n-bit symbol formed from the burst of the plurality of bits output by only a first pin of the plurality of pins, and wherein the memory controller is to:

form a second n-bit symbol from a burst of a plurality of bits output by only a second pin of the plurality of pins, and

correct the error of the memory using the first and second n-bit symbols.

11. A method comprising:

interfacing, by a memory controller, a memory comprising a plurality of pins;

forming, by the memory controller, an n-bit symbol based on a burst of a plurality of bits over time from a first pin of the plurality of pins of the memory;

forming, by the memory controller, a codeword based on a plurality of n-bit symbols, wherein the plurality of n-bit symbols includes a plurality of data symbols and a plurality of check symbols; and

correcting, by the memory controller, an error of the memory using the codeword, wherein the memory controller is to store an indication of a hard pin failure of a first pin of the memory based on a previously corrected pin failure, and tolerate a plurality of pin failures based on the stored indication, a check symbol, and erasure coding.

12. The method of claim 11 , further comprising accessing the memory based on a 72-bit wide channel, based on 64-bit data and 8-bit error-correcting code (ECC), to access a single memory module of the memory per access.

13. The method of claim 11 , further comprising applying an ECC to the codeword, based on the use of the check symbols.

14. The method of claim 13 , wherein the ECC is a Reed-Solomon code.

15. The method of claim 11 , wherein the n-bit symbol is based on the burst of the plurality of bits over time from only the first pin, the method further comprising:

forming, by the memory controller, a second n-bit symbol based on a burst of a plurality of bits over time from only a second pin of the plurality of pins,

wherein the codeword includes the first and second n-bit symbols.

16. An apparatus comprising:

a memory controller to:

interface a memory having a plurality of pins;

form a first n-bit symbol based on a burst of a plurality of bits over time output by only a first pin of the plurality of pins of the memory, and form a second n-bit symbol based on a burst of a plurality of bits over time output by only a second pin of the plurality of pins of the memory;

form a codeword based on a plurality of n-bit symbols including the first and second n-bit symbols, wherein the plurality of n-bit symbols includes a plurality of data symbols and a plurality of check symbols;

correct an error of the memory using the codeword; and

store an indication of a hard pin failure of the first pin of the memory based on a previously corrected pin failure, and tolerate a plurality of pin failures based on the stored indication, a check symbol, and erasure coding.

17. The apparatus of claim 16 , wherein the first n-bit symbol is based on a burst of n bits over time output by only the first pin, and the second n-bit symbol is based on a burst of n bits over time output by only the second pin, where n is greater than one.