IP Library Granted Patent US 10,186,658
Granted Patent B2
US 10,186,658 · App. 14/650,448 · Granted Jan 22, 2019

Memory device and method of manufacturing memory device

Inventors: Seiji Nonoguchi (Kanagawa, JP); Takeyuki Sone (Kanagawa, JP); Minoru Ikarashi (Kanagawa, JP); Hiroaki Narisawa (Tokyo, JP); Katsuhisa Aratani (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L45/122G11C5/02G11C5/025G11C13/0002H01L27/249H01L27/2427H01L27/2463H01L27/2481H01L45/00H01L45/04H01L45/08H01L45/085H01L45/1226H01L45/1266H01L45/145H01L45/146H01L45/147H01L45/1675H01L45/1683G11C2213/52G11C2213/71
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Quick Facts
Patent No.
US 10,186,658
App. No.
14/650,448
Granted
Jan 22, 2019
Kind
B2
Abstract

Provided is a storage apparatus provided with a plurality of storage elements having storage layers comprising a plurality of layers and electrodes, one layer among the plurality of layers being extended in a first direction and being shared by the plurality of storage elements disposed in the first direction, the electrodes being extended in a second direction that differs from the first direction and being shared by the plurality of storage elements disposed in the second direction.

Claims (25)

1. A memory device comprising:

a layer of conductive material, strips of the layer extend linearly in parallel along a first direction;

electrodes that extend from a substrate linearly in parallel along a second direction, the second direction is perpendicular to the first direction;

variable resistance material, a first portion of the variable resistance material is between a first one of the strips and a first one of the electrodes and a second portion of the variable resistance material is between the first one of the strips and a second one of the electrodes; and

an interlayer insulating layer between the layer and the substrate, the substrate is perpendicular to the second direction,

wherein the substrate includes a semiconductor material, the substrate touches the electrodes, and

wherein the conductive material includes a chalcogen element {S, Se, Te}, oxygen, and at least one transition metal element.

2. The memory device according to claim 1 , wherein the substrate is a silicon substrate.

3. The memory device according to claim 1 , wherein a CMOS circuit is on the substrate.

4. The memory device according to claim 1 , wherein the interlayer insulating layer is between one of the electrodes and another of the electrodes.

5. The memory device according to claim 1 , wherein the layer is an ion source layer.

6. The memory device according to claim 1 , wherein the transition metal element is a material from Group 4 titanium group{Ti, Zr, Hf}.

7. The memory device according to claim 1 , wherein the transition metal element is a material from Group 5 vanadium group{V, Nb, Ta}.

8. The memory device according to claim 1 , wherein the transition metal element is a material from Group 6 chromium group{Cr, Mo, W}.

9. The memory device according to claim 1 , wherein the variable resistance material is configured of an oxide film, a nitride film, or an oxynitride film of a metal element.

10. The memory device according to claim 1 , wherein the variable resistance material is connected in series to a non-linear element.

11. The memory device according to claim 10 , wherein the non-linear element is configured of a pn junction diode, a metal/insulator/semiconductor diode, a metal/insulator/metal diode, a metal/semiconductor/metal diode, or a varistor.

12. The memory device according to claim 1 , wherein a first portion of the variable resistance material is between the first one of the strips and the first one of the electrodes.

13. The memory device according to claim 12 , wherein the layer is between the interlayer insulating layer and a different interlayer insulating layer, the interlayer insulating layer and the different interlayer insulating layer physically touch the first portion of the variable resistance material.

14. The memory device according to claim 12 , wherein the first one of the electrodes and the first one of the strips physically touch the first portion of the variable resistance material.

15. The memory device according to claim 12 , wherein a second portion of the variable resistance material is between the first one of the strips and a second one of the electrodes.

16. The memory device according to claim 15 , wherein the first one of the electrodes and the second one of the electrodes are of a same material.

17. The memory device according to claim 15 , wherein the first one of the strips and the second one of the electrodes physically touch the second portion of the variable resistance material.

18. The memory device according to claim 15 , wherein a third portion of the variable resistance material is between the second one of the electrodes and a third one of the strips.

19. The memory device according to claim 18 , wherein the second one of the electrodes and the third one of the strips physically touch the third portion of the variable resistance material.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ZIP CODE FROM 246-0014 TO 243-0014 PREVIOUSLY RECORDED AT REEL: 039645 FRAME: 0019. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 13, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040894/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039645/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2015
From: NONOGUCHI, SEIJI; SONE, TAKEYUKI; IKARASHI, MINORU; NARISAWA, HIROAKI; ARATANI, KATSUHISA
To: SONY CORPORATION
Reel/Frame 035856/0485 →
Priority Claims (1)
JP 2012-282108 · Dec 26, 2012 · national
Continuity (1)
Related Publication 20150325628A1 · Nov 12, 2015
Cited By (1)
US 12,660,207