Cross-point memory array with access lines
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
1 . A method, comprising:
forming a via hole that extends through a stack to a conductive element, the stack comprising a target electrode;
filling the via hole with a conductive material;
removing a portion of the conductive material from the via hole to expose a dielectric buffer interposed between the via hole and the target electrode;
removing the dielectric buffer to expose the target electrode; and
filling the via hole with the conductive material to couple the target electrode with the conductive element.
2 . The method of claim 1 , wherein:
removing the dielectric buffer to expose the target electrode simultaneously exposes a second target electrode within a target electrode layer that includes the target electrode, the second target electrode being on an opposite side of the via hole relative to the target electrode.
3 . The method of claim 2 , wherein filling the via hole with the conductive material to couple the target electrode with the conductive element further comprises:
coupling the target electrode with the second target electrode.
4 . The method of claim 1 , further comprising:
forming a conformal liner at a different electrode layer within the stack.
5 . The method of claim 1 , further comprising:
forming a gap in the target electrode.
6 . The method of claim 5 , wherein forming the gap in the target electrode comprises:
anisotropically etching through the target electrode.
7 . The method of claim 5 , wherein forming the gap in the target electrode comprises:
forming a second via hole that extends through the stack to at least a target layer that includes the target electrode; and
isotropically removing, through the second via hole, a portion of the target electrode.
8 . The method of claim 1 , wherein the stack further comprises:
a first deck of memory cells; and
a second deck of memory cells positioned between the first deck and the conductive element, wherein the target electrode is in the first deck of memory cells or the second deck of memory cells.
9 . The method of claim 8 , wherein the target electrode is in the first deck of memory cells, and wherein the via hole is coupled with a second dielectric buffer interposed between the via hole and an electrode layer in the second deck of memory cells.
10 . A method, comprising:
forming a via hole that extends through a stack to a conductive element, the stack comprising a first deck of memory cells, a second deck of memory cells positioned between the first deck and the conductive element, and a target electrode in the second deck;
filling the via hole with a conductive material;
removing a first portion of the conductive material from the via hole to expose a first dielectric buffer in the first deck of memory cells;
removing a second portion of the conductive material from the via hole to expose a second dielectric buffer interposed between the via hole and the target electrode in the second deck of memory cells;
removing the second dielectric buffer to expose the target electrode in the second deck of memory cells; and
filling the via hole with the conductive material to couple the target electrode with the conductive element.
11 . The method of claim 10 , wherein removing the second portion of the conductive material further comprises:
removing, as part of an etch process, the second portion of the conductive material from a memory layer of the stack and a target electrode layer of the stack within the via hole, wherein the via hole is a first width at the memory layer of the stack and a second width at the target electrode layer based at least in part on removing the second portion of the conductive material, the second width larger than the first width.
12 . The method of claim 10 , further comprising:
forming a conformal liner at an exposed surface of the first dielectric buffer based at least in part on removing the first portion of the conductive material.
13 . The method of claim 10 , wherein:
removing the second dielectric buffer to expose the target electrode further exposes a second target electrode within a target electrode layer that includes the target electrode, the second target electrode on an opposite side of the via hole relative to the target electrode.
14 . The method of claim 13 , wherein filling the via hole with the conductive material to couple the target electrode with the conductive element further comprises:
coupling the target electrode with the second target electrode; and
coupling the second target electrode with the conductive element.
15 . The method of claim 10 , further comprising:
anisotropically etching through the target electrode or isotropically removing a portion of the target electrode based at least in part on filling the via hole with the conductive material.